Hello all, I was looking through the configuration of cache memories in the classic model, and I found that in the configs/common/Caches.py, in the L1_DCACHE class, the value writeback_clean is set to False. Nevertheless, in src/mem/cache/Caches.py it is said that: "In general this (param) should be set to True for anything but the last-level cache". Thus, is this instantiaton coherent? Because in the CacheConfig.py it is NOT set to True either.
Thanks Best regards, -- Marcos Horro Varela, BSc student, University of A Coruña (UDC) +34 618 62 67 37 http://markos-horro.com _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
