Hi Andreas, I am aiming for an Intel Xeon Phi type system where the last level cache is shared by all the cores (60+). Each core, though, has a slice close to it. Is it possible to have something like this in Gem5 SE mode?
Thanks.
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
