Hi, Maybe my question was not clear. A simpler question, does gem5 consider the same cache access latency (tag access + data block access) for both parallel and sequential modes ?
If not, where this difference is taken into account. Does someone have a part of the answer ? Thanks Cordialement / Best Regards SENNI Sophiane Ph.D. CNRS / LIRMM (www.lirmm.fr) Le 31/05/2016 à 15:01, senni sophiane a écrit : > > Hi Andreas, > > I have a question regarding the cache access mode for cache. I saw the > cache can be accessed either in parallel (tag and data arrays accessed > in parallel) or sequentially (tags accessed in parallel, only one data > array (or block) is accessed on a hit). > > By reading the "src/mem/cache/tags/base_set_assoc.hh" file, I noticed > that the number of data blocks accessed is different depending on the > cache access mode. However, I did not see where the difference in > terms of latency is taken into account. It seems that for both modes, > the cache access latency coresponds to the "hit_latency" parameter, > isn't it ? > > If so, I am not sure what does the "hit_latency" parameter represent ? > Does the "hit_latency" correspond to the tag lookup latency ? Or does > it represent the complete access cache (tag lookup latency + latency > to read out the data block) ? > > As far as I know, sequential access is slower than parallel access. > > > Thanks for your help. > > -- > Cordialement / Best Regards > > SENNI Sophiane
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