Hi Felipe,
Gem5 can simulate these, with a few caveats: i) I think pli might be misinterpreted as a prefetch into the dcache (not positive on this though) ii) If you are in FS mode, gem5 will throw away any prefetches that miss in the 64 entry TLB (SE mode doesn't simulate the TLB properly). To get around this, you need to remove the lines referring to "state.req->isPrefetch()" in src/arm/arch/tlb.cc Thanks, Sam On 2016-06-07 14:42, Felipe de Azevedo Piovezan wrote: > Hi all, > > Does anybody know whether gem5 is able to simulate the ARM instructions > pli/pld (prefetch)? > Looking at the source code, they seem to be simulated as no-ops. > > Thanks! > -- > > Felipe > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users [1] Links: ------ [1] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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