Hi Joel, thank you for investigating the issue. After some testing, I see no problem for me to just leave out the offending code path. However, it might be a good idea to mention something about this issue on the website that explains how to build a x86 kernel for Gem5. Just in case someone else wants to run a recent kernel.
Thanks Anselm > Am 10.06.2016 um 18:13 schrieb Joel Hestness <[email protected]>: > > Hi Anselm, > This makes a more sense. We can at least see why the CPU is jumping into > microcode so quickly: > > ==== faulty simulation with „verify_cpu“ code path enabled ==== > 0: system.cpu T0 : @phys_startup_64 : call 0x1a4 > 0: system.cpu T0 : @phys_startup_64.0 : CALL_NEAR_I : limm t1, > 0x1a4 : IntAlu : D=0x00000000000001a4 > 500: system.cpu T0 : @phys_startup_64.1 : CALL_NEAR_I : rdip t7, > %ctrl153, : IntAlu : D=0x0000000001000005 > 1000: system.cpu T0 : @phys_startup_64.2 : CALL_NEAR_I : st t7, > SS:[rsp + 0xfffffffffffffff8] : MemWrite : D=0x0000000001000005 > A=0xfffffffffffffff8 > 1000: Page-Fault: RIP 0x1000000: vector 14: #PF(0x2) at 0xfffffffffffffff8 > 1500: system.cpu T0 : @phys_startup_64.32890 : Microcode_ROM : slli > t4, t1, 0x4 : IntAlu : D=0x00000000000000e0 > 2000: system.cpu T0 : @phys_startup_64.32891 : Microcode_ROM : ld t2, > IDTR:[t4 + 0x8] : MemRead : D=0x0000000000000000 A=0xe8 > 2500: system.cpu T0 : @phys_startup_64.32892 : Microcode_ROM : ld t4, > IDTR:[t4] : MemRead : D=0x0000000000000000 A=0xe0 > 3000: system.cpu T0 : @phys_startup_64.32893 : Microcode_ROM : chks , > t4b, 0x3 : IntAlu : > > What's happening here is that the "call verify_cpu" instruction in the > Linux kernel assembly file (arch/x86/kernel/head_64.S) is triggering a > page-fault for an unmapped memory address. It appears the stack pointer (RSP) > is the offending register (initialized to 0?) so the stack address to where > the instruction pointer will be saved is invalid (RSP+0xfffffffffffffff8 = > 0xfffffffffffffff8). The CPU core detects the page fault and tries to jump to > the page fault handler in microcode (where it ends up in the infinite loop > with the chks instruction raising GeneralProtection faults). > > From what I can tell, gem5 assumes that startup code will set up the RSP. I > see a couple places in Linux code that do that, one of which is in the same > head_64.S file under secondary_startup_64. The RSP is also set up by firmware > and/or boot loaders (e.g. arch/x86/boot/compressed/head_64.S), which would > need the CPU to run some set up before launching into the kernel at > phys_startup_64. Gabe Black describes how gem5 short circuits boot here: > http://permalink.gmane.org/gmane.comp.emulators.m5.devel/24726. > > After this much digging, my conclusion is that it might be easiest to just > leave the "call verify_cpu" instruction out of the startup_64 function (that > is a valid assumption given that gem5 short circuits boot anyway). In order > to fix this completely, you may need to set up the simulator to launch into > firmware or a boot loader before trying to boot Linux, so that the stack and > stack pointer get set up correctly. That may be a lot of painful (and > unnecessary) work unless you have a reason to study those early parts of the > boot process. > > > Joel > > > On Fri, Jun 10, 2016 at 4:24 AM, Busse, Anselm <[email protected]> > wrote: > Hi Joel, > > thank you for the quick reply. This explanation makes sense, because the > „verify_cpu“ code seems to be the very first instructions that are now > executed by the Linux kernel. > > Please finde the requested output on the end of this mail. The faulty > simulation is the first output. I only included the first 7000 ticks as it is > already repeating after that. Let me know if I can be of further assisting > fixing this issue, not only by supplying traces but the coding part as well. > > Thanks! > Anselm > > ==== faulty simulation with „verify_cpu“ code path enabled ==== > 0: system.cpu T0 : @phys_startup_64 : call 0x1a4 > 0: system.cpu T0 : @phys_startup_64.0 : CALL_NEAR_I : limm t1, > 0x1a4 : IntAlu : D=0x00000000000001a4 > 500: system.cpu T0 : @phys_startup_64.1 : CALL_NEAR_I : rdip t7, > %ctrl153, : IntAlu : D=0x0000000001000005 > 1000: system.cpu T0 : @phys_startup_64.2 : CALL_NEAR_I : st t7, > SS:[rsp + 0xfffffffffffffff8] : MemWrite : D=0x0000000001000005 > A=0xfffffffffffffff8 > 1000: Page-Fault: RIP 0x1000000: vector 14: #PF(0x2) at 0xfffffffffffffff8 > 1500: system.cpu T0 : @phys_startup_64.32890 : Microcode_ROM : slli > t4, t1, 0x4 : IntAlu : D=0x00000000000000e0 > 2000: system.cpu T0 : @phys_startup_64.32891 : Microcode_ROM : ld t2, > IDTR:[t4 + 0x8] : MemRead : D=0x0000000000000000 A=0xe8 > 2500: system.cpu T0 : @phys_startup_64.32892 : Microcode_ROM : ld t4, > IDTR:[t4] : MemRead : D=0x0000000000000000 A=0xe0 > 3000: system.cpu T0 : @phys_startup_64.32893 : Microcode_ROM : chks , > t4b, 0x3 : IntAlu : > 3000: General-Protection: RIP 0x1000000: vector 13: #GP(0) > 3500: system.cpu T0 : @phys_startup_64.32890 : Microcode_ROM : slli > t4, t1, 0x4 : IntAlu : D=0x00000000000000d0 > 4000: system.cpu T0 : @phys_startup_64.32891 : Microcode_ROM : ld t2, > IDTR:[t4 + 0x8] : MemRead : D=0x0000000000000000 A=0xd8 > 4500: system.cpu T0 : @phys_startup_64.32892 : Microcode_ROM : ld t4, > IDTR:[t4] : MemRead : D=0x0000000000000000 A=0xd0 > 5000: system.cpu T0 : @phys_startup_64.32893 : Microcode_ROM : chks , > t4b, 0x3 : IntAlu : > 5000: General-Protection: RIP 0x1000000: vector 13: #GP(0) > 5500: system.cpu T0 : @phys_startup_64.32890 : Microcode_ROM : slli > t4, t1, 0x4 : IntAlu : D=0x00000000000000d0 > 6000: system.cpu T0 : @phys_startup_64.32891 : Microcode_ROM : ld t2, > IDTR:[t4 + 0x8] : MemRead : D=0x0000000000000000 A=0xd8 > 6500: system.cpu T0 : @phys_startup_64.32892 : Microcode_ROM : ld t4, > IDTR:[t4] : MemRead : D=0x0000000000000000 A=0xd0 > 7000: system.cpu T0 : @phys_startup_64.32893 : Microcode_ROM : chks , > t4b, 0x3 : IntAlu : > ================================================ > > > ===== working simulation without „verify_cpu“ code path ===== > 0: system.cpu T0 : @phys_startup_64 : lea rbp, DS:[rip + > 0xfffffffffffffff9] > 0: system.cpu T0 : @phys_startup_64.0 : LEA_R_P : rdip t7, > %ctrl153, : IntAlu : D=0x0000000001000007 > 500: system.cpu T0 : @phys_startup_64.1 : LEA_R_P : lea rbp, DS:[t7 > + 0xfffffffffffffff9] : IntAlu : D=0x0000000001000000 > 1500: system.cpu T0 : @phys_startup_64+7 : sub rax, 0x1000000 > 1500: system.cpu T0 : @phys_startup_64+7.0 : SUB_R_I : limm t1, > 0x1000000 : IntAlu : D=0x0000000001000000 > 2000: system.cpu T0 : @phys_startup_64+7.1 : SUB_R_I : sub rbp, rbp, > t1 : IntAlu : D=0x0000000000000000 > 3000: system.cpu T0 : @phys_startup_64+14 : mov rax, rbp > 3000: system.cpu T0 : @phys_startup_64+14.0 : MOV_R_R : mov rax, rax, > rbp : IntAlu : D=0x0000000000000000 > 3500: system.cpu T0 : @phys_startup_64+17 : and eax, 0x1fffff > 3500: system.cpu T0 : @phys_startup_64+17.0 : AND_R_I : limm t1d, > 0x1fffff : IntAlu : D=0x00000000001fffff > 4000: system.cpu T0 : @phys_startup_64+17.1 : AND_R_I : and eax, eax, > t1d : IntAlu : D=0x0000000000000000 > 4500: system.cpu T0 : @phys_startup_64+22 : test eax, eax > 4500: system.cpu T0 : @phys_startup_64+22.0 : TEST_R_R : and t0d, > eax, eax : IntAlu : D=0x0000000000000000 > 5000: system.cpu T0 : @phys_startup_64+24 : jnz 0x1a7 > 5000: system.cpu T0 : @phys_startup_64+24.0 : JNZ_I : rdip t1, > %ctrl153, : IntAlu : D=0x000000000100001e > 5500: system.cpu T0 : @phys_startup_64+24.1 : JNZ_I : limm t2, 0x1a7 > : IntAlu : D=0x00000000000001a7 > 6000: system.cpu T0 : @phys_startup_64+24.2 : JNZ_I : wrip , t1, t2 > : IntAlu : > 7000: system.cpu T0 : @phys_startup_64+30 : lea rax, DS:[rip + > 0xffffffffffffffdb] > 7000: system.cpu T0 : @phys_startup_64+30.0 : LEA_R_P : rdip t7, > %ctrl153, : IntAlu : D=0x0000000001000025 > 7500: system.cpu T0 : @phys_startup_64+30.1 : LEA_R_P : lea rax, > DS:[t7 + 0xffffffffffffffdb] : IntAlu : D=0x0000000001000000 > 8500: system.cpu T0 : @phys_startup_64+37 : shr rax, 0x2e > 8500: system.cpu T0 : @phys_startup_64+37.0 : SHR_R_I : srli rax, > rax, 0x2e : IntAlu : D=0x0000000000000000 > 9000: system.cpu T0 : @phys_startup_64+41 : jnz 0x196 > 9000: system.cpu T0 : @phys_startup_64+41.0 : JNZ_I : rdip t1, > %ctrl153, : IntAlu : D=0x000000000100002f > 9500: system.cpu T0 : @phys_startup_64+41.1 : JNZ_I : limm t2, 0x196 > : IntAlu : D=0x0000000000000196 > 10000: system.cpu T0 : @phys_startup_64+41.2 : JNZ_I : wrip , t1, t2 > : IntAlu : > 11000: system.cpu T0 : @phys_startup_64+47 : add DS:[rip + 0x64cfc2], > rbp > 11000: system.cpu T0 : @phys_startup_64+47.0 : ADD_P_R : rdip t7, > %ctrl153, : IntAlu : D=0x0000000001000036 > 11500: system.cpu T0 : @phys_startup_64+47.1 : ADD_P_R : ldst t1, > DS:[t7 + 0x64cfc2] : MemRead : D=0x0000000001577067 A=0x164cff8 > 12000: system.cpu T0 : @phys_startup_64+47.2 : ADD_P_R : add t1, t1, > rbp : IntAlu : D=0x0000000000000000 > 12500: system.cpu T0 : @phys_startup_64+47.3 : ADD_P_R : st t1, DS:[t7 > + 0x64cfc2] : MemWrite : D=0x0000000001577067 A=0x164cff8 > 13500: system.cpu T0 : @phys_startup_64+54 : add DS:[rip + 0x577fb3], > rbp > 13500: system.cpu T0 : @phys_startup_64+54.0 : ADD_P_R : rdip t7, > %ctrl153, : IntAlu : D=0x000000000100003d > 14000: system.cpu T0 : @phys_startup_64+54.1 : ADD_P_R : ldst t1, > DS:[t7 + 0x577fb3] : MemRead : D=0x0000000001578063 A=0x1577ff0 > 14500: system.cpu T0 : @phys_startup_64+54.2 : ADD_P_R : add t1, t1, > rbp : IntAlu : D=0x0000000000000000 > 15000: system.cpu T0 : @phys_startup_64+54.3 : ADD_P_R : st t1, DS:[t7 > + 0x577fb3] : MemWrite : D=0x0000000001578063 A=0x1577ff0 > 16000: system.cpu T0 : @phys_startup_64+61 : add DS:[rip + 0x577fb4], > rbp > 16000: system.cpu T0 : @phys_startup_64+61.0 : ADD_P_R : rdip t7, > %ctrl153, : IntAlu : D=0x0000000001000044 > 16500: system.cpu T0 : @phys_startup_64+61.1 : ADD_P_R : ldst t1, > DS:[t7 + 0x577fb4] : MemRead : D=0x0000000001579067 A=0x1577ff8 > 17000: system.cpu T0 : @phys_startup_64+61.2 : ADD_P_R : add t1, t1, > rbp : IntAlu : D=0x0000000000000000 > 17500: system.cpu T0 : @phys_startup_64+61.3 : ADD_P_R : st t1, DS:[t7 > + 0x577fb4] : MemWrite : D=0x0000000001579067 A=0x1577ff8 > 18500: system.cpu T0 : @phys_startup_64+68 : add DS:[rip + 0x579f85], > rbp > 18500: system.cpu T0 : @phys_startup_64+68.0 : ADD_P_R : rdip t7, > %ctrl153, : IntAlu : D=0x000000000100004b > 19000: system.cpu T0 : @phys_startup_64+68.1 : ADD_P_R : ldst t1, > DS:[t7 + 0x579f85] : MemRead : D=0x000000000157a067 A=0x1579fd0 > 19500: system.cpu T0 : @phys_startup_64+68.2 : ADD_P_R : add t1, t1, > rbp : IntAlu : D=0x0000000000000000 > 20000: system.cpu T0 : @phys_startup_64+68.3 : ADD_P_R : st t1, DS:[t7 > + 0x579f85] : MemWrite : D=0x000000000157a067 A=0x1579fd0 > 21000: system.cpu T0 : @phys_startup_64+75 : lea rdi, DS:[rip + > 0xffffffffffffffae] > 21000: system.cpu T0 : @phys_startup_64+75.0 : LEA_R_P : rdip t7, > %ctrl153, : IntAlu : D=0x0000000001000052 > 21500: system.cpu T0 : @phys_startup_64+75.1 : LEA_R_P : lea rdi, > DS:[t7 + 0xffffffffffffffae] : IntAlu : D=0x0000000001000000 > 22500: system.cpu T0 : @phys_startup_64+82 : lea rbx, DS:[rip + > 0x64bfa7] > 22500: system.cpu T0 : @phys_startup_64+82.0 : LEA_R_P : rdip t7, > %ctrl153, : IntAlu : D=0x0000000001000059 > 23000: system.cpu T0 : @phys_startup_64+82.1 : LEA_R_P : lea rbx, > DS:[t7 + 0x64bfa7] : IntAlu : D=0x000000000164c000 > 23500: system.cpu T0 : @phys_startup_64+89 : mov rax, rdi > 23500: system.cpu T0 : @phys_startup_64+89.0 : MOV_R_R : mov rax, rax, > rdi : IntAlu : D=0x0000000001000000 > 24000: system.cpu T0 : @phys_startup_64+92 : shr rax, 0x27 > 24000: system.cpu T0 : @phys_startup_64+92.0 : SHR_R_I : srli rax, > rax, 0x27 : IntAlu : D=0x0000000000000000 > 24500: system.cpu T0 : @phys_startup_64+96 : lea rdx, DS:[rbx + 0x1063] > 24500: system.cpu T0 : @phys_startup_64+96.0 : LEA_R_M : lea rdx, > DS:[rbx + 0x1063] : IntAlu : D=0x000000000164d063 > 25500: system.cpu T0 : @phys_startup_64+103 : mov DS:[8*rax + rbx], rdx > 25500: system.cpu T0 : @phys_startup_64+103.0 : MOV_M_R : st rdx, > DS:[8*rax + rbx] : MemWrite : D=0x000000000164d063 A=0x164c000 > 26000: system.cpu T0 : @phys_startup_64+107 : mov DS:[8*rax + rbx + > 0x8], rdx > 26000: system.cpu T0 : @phys_startup_64+107.0 : MOV_M_R : st rdx, > DS:[8*rax + rbx + 0x8] : MemWrite : D=0x000000000164d063 A=0x164c008 > 26500: system.cpu T0 : @phys_startup_64+112 : add rax, 0x1000 > 26500: system.cpu T0 : @phys_startup_64+112.0 : ADD_R_I : limm t1, > 0x1000 : IntAlu : D=0x0000000000001000 > 27000: system.cpu T0 : @phys_startup_64+112.1 : ADD_R_I : add rdx, > rdx, t1 : IntAlu : D=0x0000000000000000 > 28000: system.cpu T0 : @phys_startup_64+119 : mov rax, rdi > 28000: system.cpu T0 : @phys_startup_64+119.0 : MOV_R_R : mov rax, > rax, rdi : IntAlu : D=0x0000000001000000 > 28500: system.cpu T0 : @phys_startup_64+122 : shr rax, 0x1e > 28500: system.cpu T0 : @phys_startup_64+122.0 : SHR_R_I : srli rax, > rax, 0x1e : IntAlu : D=0x0000000000000000 > 29500: system.cpu T0 : @phys_startup_64+126 : and eax, 0x1ff > 29500: system.cpu T0 : @phys_startup_64+126.0 : AND_R_I : limm t1d, > 0x1ff : IntAlu : D=0x00000000000001ff > 30000: system.cpu T0 : @phys_startup_64+126.1 : AND_R_I : and eax, > eax, t1d : IntAlu : D=0x0000000000000000 > 31000: system.cpu T0 : @phys_startup_64+131 : mov DS:[8*rax + rbx + > 0x1000], rdx > 31000: system.cpu T0 : @phys_startup_64+131.0 : MOV_M_R : st rdx, > DS:[8*rax + rbx + 0x1000] : MemWrite : D=0x000000000164e063 A=0x164d000 > 31500: system.cpu T0 : @phys_startup_64+139 : inc edi > 31500: system.cpu T0 : @phys_startup_64+139.0 : INC_R : addi eax, eax, > 0x1 : IntAlu : D=0x0000000000000000 > 32500: system.cpu T0 : @phys_startup_64+141 : and eax, 0x1ff > 32500: system.cpu T0 : @phys_startup_64+141.0 : AND_R_I : limm t1d, > 0x1ff : IntAlu : D=0x00000000000001ff > 33000: system.cpu T0 : @phys_startup_64+141.1 : AND_R_I : and eax, > eax, t1d : IntAlu : D=0x0000000000000000 > 34000: system.cpu T0 : @phys_startup_64+146 : mov DS:[8*rax + rbx + > 0x1000], rdx > 34000: system.cpu T0 : @phys_startup_64+146.0 : MOV_M_R : st rdx, > DS:[8*rax + rbx + 0x1000] : MemWrite : D=0x000000000164e063 A=0x164d008 > 35000: system.cpu T0 : @phys_startup_64+154 : add rax, 0x2000 > 35000: system.cpu T0 : @phys_startup_64+154.0 : ADD_R_I : limm t1, > 0x2000 : IntAlu : D=0x0000000000002000 > 35500: system.cpu T0 : @phys_startup_64+154.1 : ADD_R_I : add rbx, > rbx, t1 : IntAlu : D=0x0000000000000000 > 36000: system.cpu T0 : @phys_startup_64+161 : mov rax, rdi > 36000: system.cpu T0 : @phys_startup_64+161.0 : MOV_R_R : mov rax, > rax, rdi : IntAlu : D=0x0000000001000000 > 36500: system.cpu T0 : @phys_startup_64+164 : shr rdi, 0x15 > 36500: system.cpu T0 : @phys_startup_64+164.0 : SHR_R_I : srli rdi, > rdi, 0x15 : IntAlu : D=0x0000000000000000 > 37000: system.cpu T0 : @phys_startup_64+168 : add rax, 0xe3 > 37000: system.cpu T0 : @phys_startup_64+168.0 : ADD_R_I : limm t1, > 0xe3 : IntAlu : D=0x00000000000000e3 > 37500: system.cpu T0 : @phys_startup_64+168.1 : ADD_R_I : add rax, > rax, t1 : IntAlu : D=0x0000000000000000 > 38500: system.cpu T0 : @phys_startup_64+174 : lea rcx, DS:[rip + > 0x785f4a] > 38500: system.cpu T0 : @phys_startup_64+174.0 : LEA_R_P : rdip t7, > %ctrl153, : IntAlu : D=0x00000000010000b5 > 39000: system.cpu T0 : @phys_startup_64+174.1 : LEA_R_P : lea rcx, > DS:[t7 + 0x785f4a] : IntAlu : D=0x0000000001785fff > 40000: system.cpu T0 : @phys_startup_64+181 : shr rcx, 0x15 > 40000: system.cpu T0 : @phys_startup_64+181.0 : SHR_R_I : srli rcx, > rcx, 0x15 : IntAlu : D=0x0000000000000001 > 40500: system.cpu T0 : @phys_startup_64+185 : sub rcx, rdi > 40500: system.cpu T0 : @phys_startup_64+185.0 : SUB_R_R : sub rcx, > rcx, rdi : IntAlu : D=0x0000000000000000 > 41000: system.cpu T0 : @phys_startup_64+188 : inc edi > 41000: system.cpu T0 : @phys_startup_64+188.0 : INC_R : addi ecx, ecx, > 0x1 : IntAlu : D=0x0000000000000000 > 42000: system.cpu T0 : @phys_startup_64+190 : and rax, 0x1ff > 42000: system.cpu T0 : @phys_startup_64+190.0 : AND_R_I : limm t1, > 0x1ff : IntAlu : D=0x00000000000001ff > 42500: system.cpu T0 : @phys_startup_64+190.1 : AND_R_I : and rdi, > rdi, t1 : IntAlu : D=0x0000000000000000 > 43500: system.cpu T0 : @phys_startup_64+197 : mov DS:[8*rdi + rbx], rax > 43500: system.cpu T0 : @phys_startup_64+197.0 : MOV_M_R : st rax, > DS:[8*rdi + rbx] : MemWrite : D=0x00000000010000e3 A=0x164e040 > 44000: system.cpu T0 : @phys_startup_64+201 : inc rdi > 44000: system.cpu T0 : @phys_startup_64+201.0 : INC_R : addi rdi, rdi, > 0x1 : IntAlu : D=0x0000000000000000 > 45000: system.cpu T0 : @phys_startup_64+204 : add rax, 0x200000 > 45000: system.cpu T0 : @phys_startup_64+204.0 : ADD_R_I : limm t1, > 0x200000 : IntAlu : D=0x0000000000200000 > 45500: system.cpu T0 : @phys_startup_64+204.1 : ADD_R_I : add rax, > rax, t1 : IntAlu : D=0x0000000000000000 > 46000: system.cpu T0 : @phys_startup_64+210 : dec edi > 46000: system.cpu T0 : @phys_startup_64+210.0 : DEC_R : subi ecx, ecx, > 0x1 : IntAlu : D=0x0000000000000000 > 46500: system.cpu T0 : @phys_startup_64+212 : jnz 0xffffffffffffffe8 > 46500: system.cpu T0 : @phys_startup_64+212.0 : JNZ_I : rdip t1, > %ctrl153, : IntAlu : D=0x00000000010000d6 > 47000: system.cpu T0 : @phys_startup_64+212.1 : JNZ_I : limm t2, > 0xffffffffffffffe8 : IntAlu : D=0xffffffffffffffe8 > 47500: system.cpu T0 : @phys_startup_64+212.2 : JNZ_I : wrip , t1, t2 > : IntAlu : > 48500: system.cpu T0 : @phys_startup_64+190 : and rax, 0x1ff > 48500: system.cpu T0 : @phys_startup_64+190.0 : AND_R_I : limm t1, > 0x1ff : IntAlu : D=0x00000000000001ff > 49000: system.cpu T0 : @phys_startup_64+190.1 : AND_R_I : and rdi, > rdi, t1 : IntAlu : D=0x0000000000000000 > 50000: system.cpu T0 : @phys_startup_64+197 : mov DS:[8*rdi + rbx], rax > 50000: system.cpu T0 : @phys_startup_64+197.0 : MOV_M_R : st rax, > DS:[8*rdi + rbx] : MemWrite : D=0x00000000012000e3 A=0x164e048 > ================================================ > > > Am 09.06.2016 um 20:06 schrieb Joel Hestness <[email protected]>: > > > > Hi Anselm, > > It looks like the problem may be with how the Chks microop behaves when > > it receives an input it does not usually expect (e.g. values found in older > > kernel versions). Before starting the kernel, gem5 executed microcode as in > > your trace, and then jumps into the kernel at the appropriate location. > > Chks requires some initial processor settings to be correct, and may raise > > a GeneralProtection fault if the SegIntGateCheck finds incorrect CPU > > register values (see src/arch/x86/isa/microops/regop.isa). > > > > To help us better understand the problem, could you do the following?: > > 1) Re-run the failing simulation with more debug flags: LocalApic and > > Faults (i.e. --debug-flag=Exec,LocalApic,Faults). This will help us know > > if, in fact, Chks is raising a fault, and will give us something to compare > > against for the following: > > 2) Re-run the simulation with the kernel that comments out verify_cpu, > > and use the same debug flags (--debug-flag=Exec,LocalApic,Faults) > > > > Then, copy the simulator debug information for the first ~50k simulated > > ticks into a reply on this thread (note: the numbers at the start of each > > debug output line are the simulation's ticks). This should help us identify > > what the simulator is doing differently in each case. > > > > Thanks! > > Joel > > > > > > > > On Thu, Jun 9, 2016 at 6:41 AM, Busse, Anselm <[email protected]> > > wrote: > > Hi everyone, > > > > the first thing I have to say is that I am completely new to Gem5, so > > please excuse me when I lack some expertise regarding it. > > > > I have some trouble running the x86_64 Linux kernel v4.4. Apparently with > > this version some CPU verification was introduced with > > „arch/x86/kernel/verify_cpu.S“. It seems that Gem5 gets stuck, when I > > execute the kernel in FS mode. I did some tracing and was able to observe > > that it gets stuck in a loop (4 lines repeating forever): > > > > 1500: system.cpu T0 : @phys_startup_64.32890 : Microcode_ROM : slli > > t4, t1, 0x4 : IntAlu : D=0x00000000000000e0 > > 2000: system.cpu T0 : @phys_startup_64.32891 : Microcode_ROM : ld > > t2, IDTR:[t4 + 0x8] : MemRead : D=0x0000000000000000 A=0xe8 > > 2500: system.cpu T0 : @phys_startup_64.32892 : Microcode_ROM : ld > > t4, IDTR:[t4] : MemRead : D=0x0000000000000000 A=0xe0 > > 3000: system.cpu T0 : @phys_startup_64.32893 : Microcode_ROM : chks > > , t4b, 0x3 : IntAlu : > > 3500: system.cpu T0 : @phys_startup_64.32890 : Microcode_ROM : slli > > t4, t1, 0x4 : IntAlu : D=0x00000000000000d0 > > 4000: system.cpu T0 : @phys_startup_64.32891 : Microcode_ROM : ld > > t2, IDTR:[t4 + 0x8] : MemRead : D=0x0000000000000000 A=0xd8 > > 4500: system.cpu T0 : @phys_startup_64.32892 : Microcode_ROM : ld > > t4, IDTR:[t4] : MemRead : D=0x0000000000000000 A=0xd0 > > 5000: system.cpu T0 : @phys_startup_64.32893 : Microcode_ROM : chks > > , t4b, 0x3 : IntAlu : > > > > The problem is fixed, when I comment out the verify_cpu code, but I would > > really like to fix the problem for real. Unfortunately, like I said, I’m > > brand new to Gem5, so I have no idea how to proceed further. Maybe someone > > can give me a hint how I can investigate that problem further. > > > > Thanks and Regards, > > Anselm > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > > > -- > > Joel Hestness > > PhD Candidate, Computer Architecture > > Dept. of Computer Science, University of Wisconsin - Madison > > http://pages.cs.wisc.edu/~hestness/ > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > -- > Joel Hestness > PhD Candidate, Computer Architecture > Dept. of Computer Science, University of Wisconsin - Madison > http://pages.cs.wisc.edu/~hestness/ > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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