Hi Jason, after looking into x86 SSE instructions in gem5 I have figured
out that most of them are decoded into micro-ops which operate on floating
point registers. Also, I looked at the discussion at the following link:

http://comments.gmane.org/gmane.comp.emulators.m5.devel/4404

After going through these, will I be wrong in concluding that labelling of
SSE micro-ops as floating point micro-ops is correct for most of the cases
? I'm not sure how close is this implementation to real x86 processors,
though.



On Wed, Jun 22, 2016 at 2:12 PM, Ayaz Akram <aaq...@gmail.com> wrote:

> Thanks Jason. I'll try to fix it and possibly submit a patch.
>
>
>
> On Wed, Jun 22, 2016 at 9:30 AM, Jason Lowe-Power <ja...@lowepower.com>
> wrote:
>
>> To directly answer your question: The labeling of instruction in gem5 is
>> not accurate at all. Feel free to fix the labeling and submit a patch to
>> reviews.gem5.org, though! We'd welcome the fixes.
>>
>> BTW, you're correct that SIMD instructions are labeled as floating point
>> instructions. I've noticed that too.
>>
>> Cheers,
>> Jason
>>
>> On Tue, Jun 21, 2016 at 3:42 PM Ayaz Akram <aaq...@gmail.com> wrote:
>>
>>> I am running a small C program on gem5. Disassembled binary of the
>>> program shows a lot of SSE instructions, but simulator's output stats.txt
>>> does not show any SIMD operation type committed. On generating the
>>> execution trace from gem5, I can see that those SSE instructions are
>>> decoded into operations and labelled as FloatAdd or other similar
>>> instructions. My question is, how accurate is the labelling of operations
>>> in gem5 for x86 ? I mean it seems a bit misleading to see that no SIMD
>>> instructions are committed , while the benchmark has some of them.
>>>
>>> Thanks
>>> _______________________________________________
>>> gem5-users mailing list
>>> gem5-users@gem5.org
>>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>>
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>
>
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