Hello, I am trying to model the SPARC T1 processor in GEM5 SE. Now, to properly configure the Architectural Simulator for Performance simulation, I need to mimic the configuration to as much as possible with the real Hardware from the Published data of the SPARC T1.
I started by looking at the Status Matrix published in GEM5 website to get an idea what is supported for SPARC (http://www.m5sim.org/Status_Matrix) and noticed that SPARC does not have support for the InOrderCPU. · Now to my knowledge, SPARC T1 is an InOrder pipelined model CPU, so based on that, is the chart wrong in the GEM5 website? · If InOrderCPU (which is the minor CPU in GEM5 now) does not work for SPARC T1, have anyone in the community did some hacking either on the Minor CPU (InOrderCPU) or the O3 (OutofOrderCPU) to mimic the SPARC T1? · SPARC T1 have no Branch Prediction unit in its design (source: The UltraSPARC T1 Processor -Power Efficient Throughput Computing), so I need to disable (or trick the existing BP model) in GEM5. So far I have hardcoded the “LocalBP::lookup” function in 2bit_local.cc to “NotTaken” as the return value of the function. But that doesn’t necessarily mean it is I have disabled the BP Unit, but just becomes a static BP model. · SPARC T1 have Hardware Threads in it. Does the SPARC Core in GEM5 model this feature? If so, how can we see its performance in SE mode Simulation? So far I am able to run simulations using the O3CPU model for SPARC (with the caches/L2 etc changed to SPARC’s configuration), but this is not right, as O3 is OutofOrderCPU. I understand SPARC support is limited in the group, but anyone with some understanding on the issues could share their experience/expertise, that would nudge me in the right direction. Much Appreciated. Monir Zaman
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