Hello, The fact that 161 works is very strange. <163 must not work at all. In gem5/ARMv8 all FP and SIMD instructions allocate 4 destination registers, to correctly mimic one phys reg of 128 bits (the rename uses 32 bits phys regs for AArch64). This means that one must set numPhysFloatRegs=4*num_regs, where num_regs is the true number of physical registers to be simulated, and at least 164.
Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-07-23 20:50 GMT+02:00 Murat Koksal <[email protected]>: > Hello, > > I noticed this problem a few days ago. I was using se.py on O3CPU (ARM) > with modified parameters, and I noticed that the simulation was extremely > slow (According to the stats file in about 5 minutes less than 100 > instructions were fetched.) I started testing each one of the processor > parameters individually and found out that when I set cpu.numPhysFloatRegs > to the lowest possible value this problem occurs. If I set it to anything > more than the lowest possible value, it works at expected speeds. > > Lower limit for the number of physical floating point registers is set by > an assert statement in src/cpu/o3/cpu.cc: > > assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); > > For ARM, NumFloatRegs is defined as 160 in src/arch/arm/registers.hh (128 > NumFloatV8ArchRegs + 32 NumFloatSpecialRegs). When I set numPhysFloatRegs > to 160 the simulation becomes impractically slow. When I set it to 161 or > more, it goes back to normal speed. > > Is this a known problem? I haven't seen anything in the mailing list about > it. > > Thanks. > -Murat. > > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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