Hi Monir, First of all, the status matrix is quite out of date. I honestly have no idea what the current status of most of the CPU/architectures are. For instance, we deprecated and then removed the InOrder CPU months ago. You won't be able to find that in the current gem5 branch. Additionally, many of the combinations of CPU-arch-Ruby just have never been tested, so we don't know if they work or not.
Currently the MinorCPU is the only in-order model we have. It was originally written to work with ARM, but I've had luck using it with x86 as well. I have no idea if it will work with SPARC or not. As far as multithreading goes... I've never tried to use the multithreading support, so I don't know what the current status is. This is a characteristic of the CPU model, not the ISA. So you'll have to see if the CPU model you want to use support multithreading. For assigning multiple workloads in SE mode, you should just be able to set the "workload" of each CPU to a unique "LiveProcess" and things should work, as long as you're not trying to run an application where these two processes communicate. Jason PS: If you reply directly to emails instead of the digests it's easier to follow the email thread, for both us and people who may find this conversation later. On Tue, Aug 2, 2016 at 11:43 AM Zaman, Monir <[email protected]> wrote: > Hello Jason, > Thanks for your reply. I have few questions needs to be answered: > - I looked into the Status Matrix (http://www.m5sim.org/Status_Matrix), > and it says the Memory System for SPARC does not work with InOrder (or > MinorCPU) CPU. So in that case how will I be able to run anything using the > MinorCPU for SPARC. I had tried compiling the SPARC with MinorCPU option, > but it didn’t work when I tried to run the helloworld program. Basically it > said unavailable option. > - Next, I looked into the “To Do List” for InOrder CPU, and it says SPARC > is partially implemented, what does it mean? > - For Threading in SPARC, is it same as running multiple workloads in > multiple CPUs in the SE mode? I have not yet seen any SPARC implementation > in GEM5 using the InOrder Detailed CPU. Other than the timing of the > pipeline stages, can I be functionally correct by running the SPARC in > “timing” model of the “SimpleCPU” and calculate the power using McPAT? > - For assigning multiple workloads in SE mode, I have tried just simply > increasing “np” to 2 and running 2 “hello_world” binaries. In the stats > file, I see only data for “cpu0” and “cpu1” seems to be idle (all 0). > - Where should I be looking at to “Detailed MinorCPU” implementation for > SPARC? > > /Monir > > On 8/2/16, 11:00 AM, "gem5-users on behalf of [email protected]" > <[email protected] on behalf of [email protected]> > wrote: > > Send gem5-users mailing list submissions to > [email protected] > > To subscribe or unsubscribe via the World Wide Web, visit > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > or, via email, send a message with subject or body 'help' to > [email protected] > > You can reach the person managing the list at > [email protected] > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of gem5-users digest..." > > > Today's Topics: > > 1. Making a C application work on multiple cores with gem5 > (anoir nechi) > 2. Making a C application work on multiple cores with gem5 > (anoir nechi) > 3. Virtual to Physical Address in ARMv8 FS Classic Memory > (Vanchinathan Venkataramani) > 4. Re: Making a C application work on multiple cores with > gem5 > (Jason Lowe-Power) > 5. Re: Making a C application work on multiple cores with > gem5 > (Jason Lowe-Power) > 6. Re: Physmem in SE Mode (Jason Lowe-Power) > 7. Re: Making a C application work on multiple cores with > gem5 > (anoir nechi) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Tue, 2 Aug 2016 11:17:55 +0200 > From: anoir nechi <[email protected]> > To: gem5 users mailing list <[email protected]>, [email protected] > Subject: [gem5-users] Making a C application work on multiple cores > with gem5 > Message-ID: > <CAPthOnW-XwapOwjRX13iD= > [email protected]> > Content-Type: text/plain; charset="utf-8" > > hello > > I am new with gem5 simulator. I have a C application that i want to > make it > run faster. So the first thing I've done is to optimize it using > several > techniques like loop unrolling and SIMD. And the next step, i intend to > make it work on *multiple cores* (*X86* and *ARM*) for that i must use > the > gem5 simulator. > > The application is for Radix4 computing. For now I've succeeded to > make it > work on one core systems for *X86* and *ARM* but, now i want to make it > work on 4, 16, ... cores X86 or ARM. > > could someone give me some hints or show me the right way to do this? > Thank > you > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: < > http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20160802/59cd9c14/attachment-0002.html > > > > ------------------------------ > > Message: 2 > Date: Tue, 2 Aug 2016 11:17:55 +0200 > From: anoir nechi <[email protected]> > To: gem5 users mailing list <[email protected]>, [email protected] > Subject: [gem5-users] Making a C application work on multiple cores > with gem5 > Message-ID: > <CAPthOnW-XwapOwjRX13iD= > [email protected]> > Content-Type: text/plain; charset="utf-8" > > hello > > I am new with gem5 simulator. I have a C application that i want to > make it > run faster. So the first thing I've done is to optimize it using > several > techniques like loop unrolling and SIMD. And the next step, i intend to > make it work on *multiple cores* (*X86* and *ARM*) for that i must use > the > gem5 simulator. > > The application is for Radix4 computing. For now I've succeeded to > make it > work on one core systems for *X86* and *ARM* but, now i want to make it > work on 4, 16, ... cores X86 or ARM. > > could someone give me some hints or show me the right way to do this? > Thank > you > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: < > http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20160802/59cd9c14/attachment-0003.html > > > > ------------------------------ > > Message: 3 > Date: Tue, 2 Aug 2016 21:07:17 +0800 > From: Vanchinathan Venkataramani <[email protected]> > To: gem5 users mailing list <[email protected]> > Subject: [gem5-users] Virtual to Physical Address in ARMv8 FS Classic > Memory > Message-ID: > < > cak8ug3axep2gmymvjjxkxja0ysjxtjptdabohphnlhh4bu+...@mail.gmail.com> > Content-Type: text/plain; charset="utf-8" > > Hi all > > I am currently running an application on 64 core ARMv8 FS with Classic > Memory with individual L1 D and I Cache and unified L2 cache. > > On looking at the cache memory trace, two virtual addresses, one from > Kernel space (e.g. 0xffffffc071a63400) and one from application space > (e.g. > 0x915400) are mapped to the same physical address (e.g. 0xf1a63400) > > The *kernel memory access* occurs first and ends as a *cache miss*. > However, the first access to the application memory address ends up as > a *cache > hit. *I double checked with the cache trace and statistics to confirm > this. > > One explanation is that these belong to two different threads and > hence can > have the same physical address due to context switching. However, if > that > is the case, access to the application address should end up as a miss > (which is not the case). > > Any explanation is greatly appreciated. Thanks a lot in advance. > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: < > http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20160802/1417f313/attachment-0001.html > > > > ------------------------------ > > Message: 4 > Date: Tue, 02 Aug 2016 13:28:28 +0000 > From: Jason Lowe-Power <[email protected]> > To: gem5 users mailing list <[email protected]>, [email protected] > Subject: Re: [gem5-users] Making a C application work on multiple > cores with gem5 > Message-ID: > < > cafehpudoc+oj82s-9-2kzhg2tj2znrhg4-o0jj5rt1prl7q...@mail.gmail.com> > Content-Type: text/plain; charset="utf-8" > > Hello, > > If you're using full system mode (FS mode), you can use pthreads or any > other threading library just like on a real machine. If you're using > syscall emulation (SE) mode, then you can use the m5threads library > which > is a pthreads-like library (http://repo.gem5.org/m5threads/). > > If I've misunderstood your question and you want to try to use x86 and > ARM > cores simultaneously... that currently isn't supported by gem5. > > Jason > > On Tue, Aug 2, 2016 at 4:18 AM anoir nechi <[email protected]> > wrote: > > > hello > > > > I am new with gem5 simulator. I have a C application that i want to > make > > it run faster. So the first thing I've done is to optimize it using > several > > techniques like loop unrolling and SIMD. And the next step, i intend > to > > make it work on *multiple cores* (*X86* and *ARM*) for that i must > use > > the gem5 simulator. > > > > The application is for Radix4 computing. For now I've succeeded to > make it > > work on one core systems for *X86* and *ARM* but, now i want to make > it > > work on 4, 16, ... cores X86 or ARM. > > > > could someone give me some hints or show me the right way to do this? > > Thank you > > > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: < > http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20160802/75f106f1/attachment-0002.html > > > > ------------------------------ > > Message: 5 > Date: Tue, 02 Aug 2016 13:28:28 +0000 > From: Jason Lowe-Power <[email protected]> > To: gem5 users mailing list <[email protected]>, [email protected] > Subject: Re: [gem5-users] Making a C application work on multiple > cores with gem5 > Message-ID: > < > cafehpudoc+oj82s-9-2kzhg2tj2znrhg4-o0jj5rt1prl7q...@mail.gmail.com> > Content-Type: text/plain; charset="utf-8" > > Hello, > > If you're using full system mode (FS mode), you can use pthreads or any > other threading library just like on a real machine. If you're using > syscall emulation (SE) mode, then you can use the m5threads library > which > is a pthreads-like library (http://repo.gem5.org/m5threads/). > > If I've misunderstood your question and you want to try to use x86 and > ARM > cores simultaneously... that currently isn't supported by gem5. > > Jason > > On Tue, Aug 2, 2016 at 4:18 AM anoir nechi <[email protected]> > wrote: > > > hello > > > > I am new with gem5 simulator. I have a C application that i want to > make > > it run faster. So the first thing I've done is to optimize it using > several > > techniques like loop unrolling and SIMD. And the next step, i intend > to > > make it work on *multiple cores* (*X86* and *ARM*) for that i must > use > > the gem5 simulator. > > > > The application is for Radix4 computing. For now I've succeeded to > make it > > work on one core systems for *X86* and *ARM* but, now i want to make > it > > work on 4, 16, ... cores X86 or ARM. > > > > could someone give me some hints or show me the right way to do this? > > Thank you > > > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: < > http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20160802/75f106f1/attachment-0003.html > > > > ------------------------------ > > Message: 6 > Date: Tue, 02 Aug 2016 13:33:24 +0000 > From: Jason Lowe-Power <[email protected]> > To: gem5 users mailing list <[email protected]> > Subject: Re: [gem5-users] Physmem in SE Mode > Message-ID: > < > cafehpufhtfd3jcu-sc8gootdqtdnqf73bmhhqp+1vsqkewk...@mail.gmail.com> > Content-Type: text/plain; charset="utf-8" > > Hi Monir, > > The AbstractMemory class (along with the System class) implements the > physical memory of the system. When configuring gem5, if you > instantiate a > memory object (e.g., DRAMCtrl like DDR3_1600_x64) this object will > register > the physical memory with the System object. The with the DRAMCtrl, you > can > configure both the size and the location in the address space of the > physical memory. > > For configuring a system like a SPARC T1... There isn't anything out > of the > box that will "just work". You'll have to dig into the CPU options > (probably the MinorCPU since the T1 was in-order) to see if you can > enable > threading and configure it like the T1. > > Jason > > On Mon, Aug 1, 2016 at 10:31 AM Zaman, Monir <[email protected] > > > wrote: > > > Hello all, > > > > I was running the example/se.py script for my test cases, and I > don’t see > > the “physmem” stats which mimics the DRAM. I do see a 512MB value for > > memory, but how do I setup the Physical Memory (Main Memory) in the > setup? > > > > Also, how do I set up the Hardware threading to mimic the SPARC T1 > > processor? > > > > > > > > Thanks > > > > Monir > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: < > http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20160802/e3654e30/attachment-0001.html > > > > ------------------------------ > > Message: 7 > Date: Tue, 2 Aug 2016 15:47:09 +0200 > From: anoir nechi <[email protected]> > To: gem5 users mailing list <[email protected]> > Subject: Re: [gem5-users] Making a C application work on multiple > cores with gem5 > Message-ID: > < > capthonvcv_k8us+y6tkoj5nugmgcnvjbwdg7xewxlxr2_ok...@mail.gmail.com> > Content-Type: text/plain; charset="utf-8" > > Hi Jason > > for the cores not simultaneously. i read abouat what gem5 support > > so i will try for example 4 cores of x86 then 4 cores of ARM. > > And by the way do you have any idea about ARM SIMD instructions please? > > Thank you > > On Tue, Aug 2, 2016 at 3:28 PM, Jason Lowe-Power <[email protected]> > wrote: > > > Hello, > > > > If you're using full system mode (FS mode), you can use pthreads or > any > > other threading library just like on a real machine. If you're using > > syscall emulation (SE) mode, then you can use the m5threads library > which > > is a pthreads-like library (http://repo.gem5.org/m5threads/). > > > > If I've misunderstood your question and you want to try to use x86 > and ARM > > cores simultaneously... that currently isn't supported by gem5. > > > > Jason > > > > On Tue, Aug 2, 2016 at 4:18 AM anoir nechi <[email protected]> > wrote: > > > >> hello > >> > >> I am new with gem5 simulator. I have a C application that i want to > make > >> it run faster. So the first thing I've done is to optimize it using > several > >> techniques like loop unrolling and SIMD. And the next step, i > intend to > >> make it work on *multiple cores* (*X86* and *ARM*) for that i must > use > >> the gem5 simulator. > >> > >> The application is for Radix4 computing. For now I've succeeded to > make > >> it work on one core systems for *X86* and *ARM* but, now i want to > make > >> it work on 4, 16, ... cores X86 or ARM. > >> > >> could someone give me some hints or show me the right way to do > this? > >> Thank you > >> > >> _______________________________________________ > >> gem5-users mailing list > >> [email protected] > >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > -- > *Anouar NECHI* > > > *IT Engineer : Industrial systemsHigher Institute of Computer > ScienceTunis > - El Manar University* > *Phone :* *(+216) 50 311 536* > *E-mail :* *[email protected] <[email protected]>* > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: < > http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20160802/76bbdd0c/attachment-0001.html > > > > ------------------------------ > > Subject: Digest Footer > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > ------------------------------ > > End of gem5-users Digest, Vol 121, Issue 2 > ****************************************** > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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