Hi Ferran, First, for SMT support, I believe it is implemented in the O3 CPU, and you should be able to enable it by updating your CPU configuration (numThreads, see src/cpu/BaseCPU.py). However, as far as I know, SMT is not tested in our regression tests, so it's possible (likely) that there are some bugs. If I were you, I'd start with a very simple cache hierarchy and make sure that SMT support is working how you expect before moving on to configuring your cache hierarchy.
For the caches, unless the cache coherence protocol is very important to your investigation, I would suggest you use the classic cache models. These are much more easily configurable to your exact specifications. If you must use Ruby, you'll have to carefully study how Ruby is initialized in configs/ruby/Ruby.py, configs/ruby/<protocol>.py, and configs/topologies/<topology>.py where the protocol and topology are whatever you pick. Hopefuly this gets you on the right path. Cheers, Jason On Tue, Sep 6, 2016 at 8:51 AM Ferran Olid <ferran.o...@metempsy.com> wrote: > > Hi everyone, > > I am quite new at gem5 (I've barely run some simulations) and I have to > implement a full system which requires some parametrization of the CPU, > caches and so on. I will sum up very shortly what I intend to do: > - CPU: I want to simulate a superscalar processor (I am already > aware of o3) which is able to run 2 threads in each core, with a total of 2 > cores. > - Memory Hierarchy: There are 3 cache levels; 1st level is shared > among threads within one core (2 threads as mentioned before); same with > L2. L3 is shared between the two cores. > - I am trying not to use fs.py, i rather have one custom file than > using an already existing script with a large amount of comandline options > and flags. > > So far, I have decided to use Ruby with MESI_Three_Level in order to > simulate the memory hierarchy, and as I said, I am using o3 since it is the > only superscalar cpu model in gem5. However, I am not sure how to configure > these objects... I have basically two questions: > 1. Is SMT "enabled" (implemented) by default on O3? How do I specify > the number of threads per core? > 2. Using Ruby, do I need to bind the L1 caches to the cores first, > or are all the caches described in the MESI_Three_Level.* (and two level) > files? > > I have searched through the mail files, but all the posts I've found > regarding this subject are either not replied or too old (between 5 or 9 > years), so... could someone help me with this? > > Thank you in advance, > Ferran O. > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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