Hi Seshan, I'm not sure if I totally follow what you're trying to do, but I'll do my best to give you some relevant information.
In gem5, there is an AddrRange class. You can set each cache (or memory controller, or any slave port) to respond to some specific set of AddrRanges. Thus, if you wanted to have a banked cache, you can set up a crossbar between the CPU and the L1 cache, and then add a number of different cache objects that respond to different address ranges. Currently, the AddrRange class only supports simple bit-level interleaving. You can choose some bits to use for the interleaving, and some extra bit to XOR in, if you want. However, you should be able to simply create a new subclass of AddrRange that uses some arbitrary 1-to-1 function. Cheers, Jason On Thu, Oct 6, 2016 at 3:44 PM Sriseshan S <seshu6...@gmail.com> wrote: > Hi, > > Consider an alternate memory mapping, for example, every memory address X > is supposed to be f(X), where f is some one-one mapping. > > Lets say I want to observe the impact that this mapping has on cache > performance, can I do this without modifying the static binary in gem5 ARM > SE mode? > > I simply implemented such a mapping to transform each packet’s address > before it accesses the I/D cache. This promptly leads me to a page fault. > For the topology, I’ve placed my custom address mapping unit between the > i(d)cache_port and the cpu_side of i(d) cache in src/cpu/BaseCPU.py. > > I wonder if it is absolutely necessary for me to generate a new static > executable that has these transformed addresses built-in, or can I hack my > way around in gem5 ARM SE? Also, how are the globals/constants of the > binary stored/accessed by gem5? > > Any comments/pointers/references would be appreciated :) > > Best, > Seshan > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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