Dear All,

I wanted to inform you about our simulation platform called SMCSim.
SMCSim models a *Smart Memory Cube* device (an extension to the standard
Hybrid
Memory Cube, hosting a processor for near-memory-computation on its LoB
die),
attached to a complete host system-on-chip. It is designed based on the
General Memory System model of gem5 in full-system simulation mode.

The goal in the design of this platform has been to reuse the existing
components in gem5 (e.g. DMA Engines, Interconnects, DRAM Controllers) as
much as possible, and to extend them where necessary.

Here you can access the SMCSim repository:
https://iis-git.ee.ethz.ch/erfan.azarkhish/SMCSim

This package includes:
  * The Smart Memory Cube (SMC) connected to a full-system ARM host, modeled
    based on a previous stable version of gem5.
  * An ARM based Processor-in-Memory (PIM) device connected to the main LoB
    interconnect of SMC.
  * The required software stack (APIs, drivers) and user-level applications
to
    offload tasks to PIM for execution.

For more information, you can refer to the documentations provided inside
the
repository, or take a look at our recent publication:
   * Azarkhish, Erfan, et al. "Design and Evaluation of a
Processing-in-Memory
     Architecture for the Smart Memory Cube." International Conference on
     Architecture of Computing Systems. Springer International Publishing,
     2016.
     http://link.springer.com/chapter/10.1007%2F978-3-319-30695-7_2

You can freely use/modify this simulation platform as long as you follow
gem5's copyright rules, and please don't forget to cite our paper.

Thank you,
Best Regards,

-- 
Erfan Azarkhish
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEI - University of Bologna, Italy
https://www.linkedin.com/in/erfanazarkhish
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