I wanted to inform you about our simulation platform called SMCSim.
SMCSim models a *Smart Memory Cube* device (an extension to the standard
Memory Cube, hosting a processor for near-memory-computation on its LoB
attached to a complete host system-on-chip. It is designed based on the
General Memory System model of gem5 in full-system simulation mode.
The goal in the design of this platform has been to reuse the existing
components in gem5 (e.g. DMA Engines, Interconnects, DRAM Controllers) as
much as possible, and to extend them where necessary.
Here you can access the SMCSim repository:
This package includes:
* The Smart Memory Cube (SMC) connected to a full-system ARM host, modeled
based on a previous stable version of gem5.
* An ARM based Processor-in-Memory (PIM) device connected to the main LoB
interconnect of SMC.
* The required software stack (APIs, drivers) and user-level applications
offload tasks to PIM for execution.
For more information, you can refer to the documentations provided inside
repository, or take a look at our recent publication:
* Azarkhish, Erfan, et al. "Design and Evaluation of a
Architecture for the Smart Memory Cube." International Conference on
Architecture of Computing Systems. Springer International Publishing,
You can freely use/modify this simulation platform as long as you follow
gem5's copyright rules, and please don't forget to cite our paper.
Micrel Lab - Viale Carlo Pepoli 3/2 - 40123, Bologna
DEI - University of Bologna, Italy
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