Hi,
Thank you very much! I'll try this out right now.
Regards,
Ferran O.
On 13/10/16 02:47, Ayaz Akram wrote:
Hi, you can look at following patch by Fernando, to fix Arm SimdFloat
ops labelling:
http://reviews.gem5.org/r/3547/
This will be helpful in doing similar changes for x86.
On Mon, Oct 10, 2016 at 10:19 AM, Ferran Olid
<ferran.o...@metempsy.com <mailto:ferran.o...@metempsy.com>> wrote:
Hi all,
I am running a code using the x86 decoder and I have just noticed
that for "addss", "mulss", and "divss" the instructions type which
is detected by gem5 is FloatAdd (instead of FloatMul and FloatDiv
for mulss and divss). I attach an example from the debug output:
28189782: system.cpu T0 : @foo+189.0 : DIVSS_XMM_XMM : mdivf
%xmm1_low, %xmm1_low, %xmm0_low : FloatAdd : D=0x000000003faf983c
To me this looks like a bug which is quite important to fix. I
have been trying to do it though, but with no results yet. Does
someone have any clue how this can be fixed or if there is any
existent patch already? I read the documentation in gem5
(http://www.m5sim.org/X86_Instruction_decoding
<http://www.m5sim.org/X86_Instruction_decoding>) about the x86
instruction decode, but it does not quite clarify the code...
So, any ideas?
Regards,
Ferran O.
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