Hey Ashkan, The ITB and the DTB are the TLBs for the instruction and data accesses respectively. The ITB port is the port hooking up the ITB to the CPU.
I am unable to trigger the assertion you saw when I tried this out myself. What revision of gem5 are you on? I would suggest trying again with the latest version of gem5. Have you made any local changes? Having a few more details of your simulation would also help us understand this. Cheers, Swapnil Haria, Graduate Student, Dept of Computer Sciences, University of Wisconsin-Madison
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
