Hi all, It might also be worth having a look at: https://eprint.iacr.org/2015/690.pdf
The hashing used in gem5 at the moment is rudimentary in comparison to quite a few of the hashes described in the aforementioned work. Something to be very cognisant of is that the caches today are not aware that they are banked (although they could find out by inspecting their address range). Consequently you have to be very careful to make sure they don’t have a reduced entropy in the bits used for set indexing. For example, if you use address bit [7:8] to interleave between caches (banks), and these bits are also part of the set index you have effectively reduced your cache capacity. It gets more tricky with the hashing as there is some entropy lost, but it’s not confined to just slicing bits. If anyone has any good ideas on how to solve this in the general case please say so. We have exactly the same problem in the multi-channel DRAM controller. What bits to throw away, if any? Andreas From: gem5-users <[email protected]<mailto:[email protected]>> on behalf of anoir nechi <[email protected]<mailto:[email protected]>> Reply-To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Date: Tuesday, 25 October 2016 at 23:50 To: gem5 users mailing list <[email protected]<mailto:[email protected]>> Subject: Re: [gem5-users] Create separate L2 cache for each CPU Thank you, Jason, you are a saver On Wed, Oct 26, 2016 at 12:15 AM, Jason Lowe-Power <[email protected]<mailto:[email protected]>> wrote: Hi Anoir, You can also look at this script: https://github.com/powerjg/gem5/blob/devel/simplefs/configs/myconfigs/system/caches.py It should be very simple to do what you're suggesting. You just need to create the cache and crossbar objects and hook them up. Pretty much any topology you can think of is supported. Cheers, Jason On Mon, Oct 24, 2016, 9:32 AM Rodrigo Cataldo <[email protected]<mailto:[email protected]>> wrote: Hello Anoir Nechi, take a look at this patch: http://reviews.gem5.org/r/3506/ best regards On Fri, Oct 21, 2016 at 2:57 PM, anoir nechi <[email protected]<mailto:[email protected]>> wrote: Hi I managed to create a config script simulating 4 cores with a unified L2 ( see attached figure ) But I wonder if it is possible to create a system with separate L2 caches each specified for one core ? Has anyone an idea about it? kind regards -- Anouar NECHI IT Engineer : Industrial systems Higher Institute of Computer Science _______________________________________________ gem5-users mailing list [email protected]<mailto:[email protected]> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected]<mailto:[email protected]> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected]<mailto:[email protected]> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Anouar NECHI IT Engineer : Industrial systems Higher Institute of Computer Science Tunis - El Manar University Phone : (+216) 50 311 536 E-mail :[email protected]<mailto:[email protected]> IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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