Hello Fateme, 

I hope I got your question right, so let me try to answer. 

Short answer is gem5 o3 does not implement register forwarding. 

Long answer is that it kind of does if you keep a parameter set to one. If your 
issueToExecute latency is greater than one, then two dependent instructions 
will never execute back-to-back, 
so the processor behaves as if instructions always read operands from the PRF 
and pay issueToExecute - 1 cycles to do it (although I'm pretty sure writing to 
the PRF takes 0 cycle in the o3 model). That being said, the base 
configuration of gem5 behaves as if register forwarding is implemented because 
the issueToExecute latency is 1 (and you should leave it at that unless you 
implement forwarding and 
speculative scheduling). 

So, in a given cycle, assuming the issueToExecute latency is set to 1. 
1 - Some instructions are executed and their result become available. 
2 - Some instructions are woken-up using the newly available results. 
3 - Some instructions are scheduled for execution in issueToExecute cycles (so 
1 in our example). 

Thus, two dependent instructions are allowed to execute back-to-back (even with 
loads). So really, it's more that reading a register is free rather than having 
forwarding, but 
performance-wise, it's relatively similar. 

Arthur. 

----- Mail original -----

> De: "fami Hoseini" <[email protected]>
> À: [email protected]
> Envoyé: Mercredi 23 Novembre 2016 17:30:42
> Objet: [gem5-users] O3 CPU register forwarding

> Hi,
> I'm trying to make modifications to O3 CPU. I want to know if this cpu
> implements register forwarding? If yes, how this communication is
> implemented (It seems to me that timebuffer is not used for that purpose)?
> This question was asked before:
> https://www.mail-archive.com/[email protected]/msg02327.html
> But no answers was provided for that. Maybe I'll have a better luck to get
> the answer.

> Thank you,
> Fateme

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