Hello,
I've been testing multicore systems with CPU switching in SE mode and I have a question regarding compatibility of such system with the O3CPU. I've tested multi-threaded applications (using the m5threads lib) as well as single-threaded applications, with both the X86 and ARM ISAs. To give an example, I'll use the following command: ./build/X86/gem5.opt configs/example/se.py -c ../m5threads/tests/test___thread -o 4 -n 4 --repeat-switch=50000000 --cpu-type=detailed --caches It executes an example from m5threads, with 4 threads and 4 cores, and switches CPU every 50000000 ticks. Using the latest gem5 commit, this command executes successfully. However, if I change the switch period to 20000000, the simulation enters into an infinite loop (can't kill the simulation with ctrl^c) as soon as the first switching occurs. This behavior also occurs with single-threaded applications, as long as I have multiple cores and switching CPUs active, while using the O3CPU. If, for example, I change the CPU type to atomic it will sometimes work depending on the switching period and multi-threaded application (it may give seg fault), or work all the times with the single-threaded applications i'm using. I also ran the above command with several debug flags (mainly DRAM and cache flags) and compared it with an erroneous execution (with the infinite loop), to try to find some lead on the problem, but found nothing that looked out of the ordinary. I also tried a different memory model and interconnections, namely ruby with different protocols, different caches, etc., again with no success. Can anyone give me any insight to what the problem may be? Or even direct me on where should I look at with more attention? Thanks in advance, Miguel Tairum
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