Hi Dear Andreas, Thanks a lot due to responding my email very quickly.
the solution that came to our mind is as following:
1) set non-overlapping address ranges to each local data caches of each core.
in our configuration each core has two level local caches, and l2caches connect
to memory controller through a memory-bus.(and our simulation is done in
SE-mode)
for doing this, we found an option "addr_ranges" for caches that we want to set
non-overlapping address range to this field of each local caches.
2) Then, define new mapping algorithm in "decodeaddr()" function that is
existed in "dram_ctrl.cc" file. in this new algorithm the location of each
parts of memory are as following:(rank,row,bank,col)
according to this new mapping, the address ranges that we assigned to each
local caches in '1_step', are separated from the most significant part that
refers to rank_id.
so according to these two steps, do you think its enough for loading each each
core's process(benchmark) to different rank of memory?
i should mention that there is no dependency between core's processes. each of
them runs a single program from spec2006 benchmark suite.
i appreciate if you give me your idea about these two steps, because the ideas
that you told me seems very general and if its possible i want more detailed
plan for reaching this goal.
sincerely,
ashkan asgharzadeh
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