You may have luck using debug flags. For instance "Cache" or "CacheAll" may be useful.
However, I'm not sure if gem5 is really the right tool for the job. You may want to look into PIN and other similar instrumentation. Jason On Tue, Dec 20, 2016 at 10:42 AM ps4 lover <ps4lover011...@outlook.com> wrote: > Just want to clarify, by saying "program analysis techniques to obtain the > memory address of mem load operation", of course I mean indirect memory > load operations, since the memory addresses of direct memory access can be > read from the assembly code.... > ------------------------------ > *发件人:* gem5-users <gem5-users-boun...@gem5.org> 代表 ps4 lover < > ps4lover011...@outlook.com> > *发送时间:* 2016年12月20日 8:38:23 > > *收件人:* gem5 users mailing list > *主题:* [gem5-users] 答复: Monitoring access towards different cache line > during execution time > > > Dear Jason, > > > Thank you so much for your response, I will try to dig into the details of > implementing such monitor/probe mechanism. > > > On the other hand, I understood that I can calculate the cache line > request by dividing the memory address with cache line size. However, what > I was expecting is a little bit different from this... > > > Let's say, I have utilized some program analysis techniques to obtain the > memory address of certain memory load operations, and I have already > inferred the cache line number for such memory access by using the > calculation you mentioned. > > > Right now, what I want to do is to confirm my inference by using some > low-level hardware simulator (gem5). So basically what I am expecting, is > to *see* which cache line is accessed. I was expecting that the cache > utility of gem5 itself can confirm with me for such data, as I have already > do the calculation/analysis very highlevelly. > > > Is it possible to do so..? Sorry I am a software engineering people, and > my question/concern would be very unreasonable... If it is not possible, > just let me know, I guess I can go with that as well. Thank you! > > > > ------------------------------ > *发件人:* gem5-users <gem5-users-boun...@gem5.org> 代表 Jason Lowe-Power < > ja...@lowepower.com> > *发送时间:* 2016年12月20日 8:13:48 > *收件人:* gem5 users mailing list > *主题:* Re: [gem5-users] Monitoring access towards different cache line > during execution time > > Hello, > > You can add a CommMonitor to your memory hierarchy where ever you want to > intercept memory requests (e.g., between the CPU and the dcache for all > data cache accesses). Then, you can create a MemTraceProbe. This will > create a trace file as specified by you in the params when instantiating > the probe. It will trace all of the packets that pass through the > CommMonitor (see "ppPktReq" in comm_monitor.cc). You will probably want to > enable "with_pc" so you can also get the PC of requests. > > To convert the requests into cache line requests you can simply divide the > address by the cache line size. > > Cheers, > Jason > > On Mon, Dec 19, 2016 at 7:20 PM ps4 lover <ps4lover011...@outlook.com> > wrote: > > > Dear List, > > > > I would like to leverage `*gem5*` to monitor the cache access of > a program during the runtime. > > In particular, considering the following program in assembly code, I would > like to know, when executing the third memory access instruction (let's say > its memory address is 0x123456), which *cache line* it is accessing. > > > 0x123430: add eax, 1 > > 0x123440: mov eax, ebx > > 0x123456: load eax, [0x8042420] <----------- load memory content from > memory address 0x8042420 > > > > > The simulation is on `32-bit x86` architecture. I am using some > median-size C program for testing. I watched some tutorials to get familiar > with the basic functionality of `*gem5*`, but still have no idea how to > intercept the cache state for my need during runtime. I am aware the > existence of the probe utility, but I do find it is hard for me to start > with it, especially I would like to check the cache access regarding *certain > lines of instructions*. > > > I am a newbie to `*gem5*`, and I am actually not an expert in computer > architecture related stuff.. Sorry if it is a very trivial question.. Any > advice and suggestion would be appreciated, thank you! > > > > > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > -- > > Jason > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users -- Jason
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