Hi Jason, Sorry for the late replay. Thank you for your hint. I've used the "map" method exposed by the LiveProcess class to make my address range not cacheable, however when I run the se.py script I have this error: "(C++ object is not yet constructed, so wrapped C++ methods are unavailable.)"
Any thought on this? Thanks, Lorenzo 2016-11-21 16:09 GMT+01:00 Jason Lowe-Power <[email protected]>: > Hi Lorenzo, > > Are you trying to use [0x10000-0xFFFFF] as PIO? If so, this example might > help you figure out how to do what you want. > https://github.com/powerjg/gem5/commit/86394e326cede3be7b26eb728dd6a9 > a0a93406bf > > It's for x86, but it contains an example of how to use PIO in SE mode to > communicate from a user-mode program running on the guest into the > simulator. > > Cheers, > Jason > > On Mon, Nov 21, 2016 at 8:22 AM Swapnil Haria <[email protected]> > wrote: > >> Hey Lorenzo, >> >> Just to see if I understand your question, you want to have uncacheable >> address range 0x10000-0xFFFFF in physical memory and not virtual memory? >> >> I hope you realize that accesses to physical memory not actually mapped >> to DRAM is only allowed for devices. I am guessing that you don't just want >> memory in that range, for which you simply have to increase the memory size >> (using --mem-size=2GB, if you are using example scripts). >> >> For having an uncacheable region (for devices), you could try this - in >> src/arch/arm/process.cc, in ArmLiveProcess32/64::initState() >> >> MultiLevelPageTable<PageTableOps> *pt = >> dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable); >> >> pt->map(<Virtual Address>, <Physical Address>, <Region Size>, <bool >> cacheable>); >> >> Check out src/mem/pagetable.hh for the map function, and >> src/arch/x86/process.cc and src/sim/process.cc for more information about >> this. >> >> >> Cheers, >> Swapnil Haria, >> Graduate Student, >> Dept of Computer Sciences, >> University of Wisconsin-Madison >> >> On Fri, Nov 18, 2016 at 3:47 AM, Lorenzo Zuolo <[email protected]> wrote: >> >> Hi everybody, >> >> I have a very stupid question. >> I'm new in gem5 and I would like to understand how to make an address >> region uncacheable with ARM architecture in se mode. >> Problem is. I would like to have the possibility to access an address >> outside the dram range from a c program I'm executing in SE mode. >> Example is: >> Dram range is [0x0-0xFFFF] >> Desired address region is: [0x10000-0xFFFFF] >> >> In the c program I'm running on the core I would like to be able to do >> something like this: >> >> int main { >> char *reg=(char*)0x10000 //pointer to non cacheable memory region >> >> printf("value is %d\n",*reg); >> } >> >> Any thought on that? >> >> Thanks in advance >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >> >> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Lorenzo Zuolo, Ph.D. PostDoc position Università degli studi di Ferrara Dip. di Ingegneria (ENDIF) Via Saragat n°1 44122 Ferrara Fe Italy Office: 304 Phone: +39-0532-974891 Skype: lorenzo.zuolo
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
