Hello everyone,
I am attempting to create an L3 cache to run in FS mode with the ARM
detailed processor; however, I am encountering an error when trying to run the
simulator. When I try run the simulator, the following occurs:
--BEGIN TERMINAL--
$:~/Documents/gem5/gem5$ sudo build/ARM/gem5.opt configs/example/fs.py
--kernel=/home/suchy/Documents/gem5/gem5/Benchmark/asimBenchmark/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
--dtb-file=/home/suchy/Documents/gem5/gem5/Benchmark/asimBenchmark/binaries/vexpress-v2p-ca15-tc1.dtb
--disk-image=/home/suchy/Documents/gem5/gem5/Benchmark/asimBenchmark/disks/ARMv7a-ICS-Android.SMP.Asimbench-v3.img
--script=/home/suchy/Documents/gem5/gem5/Benchmark/asimBenchmark/scripts/ttpod.rcS
--os-type=android-ics --mem-size=256MB --machine-type=RealView_PBX --caches
--l3cache
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Feb 2 2017 23:49:17
gem5 started Feb 2 2017 23:56:43
gem5 executing on SmallButMIghty, pid 11798
command line: build/ARM/gem5.opt configs/example/fs.py
--kernel=/home/suchy/Documents/gem5/gem5/Benchmark/asimBenchmark/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
--dtb-file=/home/suchy/Documents/gem5/gem5/Benchmark/asimBenchmark/binaries/vexpress-v2p-ca15-tc1.dtb
--disk-image=/home/suchy/Documents/gem5/gem5/Benchmark/asimBenchmark/disks/ARMv7a-ICS-Android.SMP.Asimbench-v3.img
--script=/home/suchy/Documents/gem5/gem5/Benchmark/asimBenchmark/scripts/ttpod.rcS
--os-type=android-ics --mem-size=256MB --machine-type=RealView_PBX --caches
--l3cache
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/home/suchy/Documents/gem5/gem5/src/python/m5/main.py", line 400, in
main
exec filecode in scope
File "configs/example/fs.py", line 341, in <module>
test_sys = build_test_system(np)
File "configs/example/fs.py", line 230, in build_test_system
CacheConfig.config_cache(options, test_sys)
File "/home/suchy/Documents/gem5/gem5/configs/common/CacheConfig.py", line
195, in config_cache
system.cpu[i].connectAllPorts(system.cpu[i].tol3bus, system.membus)
File "/home/suchy/Documents/gem5/gem5/src/python/m5/SimObject.py", line 1095,
in __getattr__
raise AttributeError, err_string
AttributeError: object 'O3_ARM_v7a_3' has no attribute 'tol3bus'
(C++ object is not yet constructed, so wrapped C++ methods are unavailable.)
--END TERMINAL--
I cannot track down where I go about adding the tol3bus to get past this stage.
Is there anyone who can recommend where to look? Also, I have my default
processor set to detailed_arm.
The following are also my CacheConfig.Py, O3_ARM-V7a.Py, and Caches.Py files:
Side note: I am also trying to create a victim cache, but it encounters the
same issue. SO if you see a vcache or anything like that, please feel free to
ignore it
--Begin CacheConfig.Py--
import m5
from m5.objects import *
from Caches import *
from O3_ARM_v7a import *
def config_cache(options, system):
if options.external_memory_system and (options.caches or options.l2cache or
options.l3cache or options.vcache):
print "External caches and internal caches are exclusive options.\n"
sys.exit(1)
if options.external_memory_system:
ExternalCache = ExternalCacheFactory(options.external_memory_system)
# Set the cache line size of the system
system.cache_line_size = options.cacheline_size
# If elastic trace generation is enabled, make sure the memory system is
# minimal so that compute delays do not include memory access latencies.
# Configure the compulsory L1 caches for the O3CPU, do not configure
# any more caches.
if options.l2cache and options.elastic_trace_en:
fatal("When elastic trace is enabled, do not configure L2 caches.")
if options.cpu_type == "arm_detailed":
#try:
#from O3_ARM_v7a import *
# except:
# print "arm_detailed is unavailable. Did you compile the O3 model?"
# sys.exit(1)
dcache_class, icache_class, l2_cache_class, l3_cache_class,
v_cache_class, walk_cache_class = \
O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2, O3_ARM_v7aL3,
O3_ARM_v7aV, \
O3_ARM_v7aWalkCache
else:
dcache_class, icache_class, l2_cache_class, l3_cache_class,
v_cache_class, walk_cache_class = \
L1_DCache, L1_ICache, L2Cache, L3Cache, VCache, None
if buildEnv['TARGET_ISA'] == 'x86':
walk_cache_class = PageTableWalkerCache
if options.l2cache:
# Provide a clock for the L2 and the L1-to-L2 bus here as they
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs.
system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
assoc=options.l2_assoc)
system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
#Added L3 and VCache
if options.l3cache:
system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l3_size,assoc=options.l3_assoc)
system.tol3bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.l3.cpu_side = system.tol3bus.master
system.l3.mem_side = system.membus.slave
#
if options.vcache:
system.v = v_cache_class(clk_domain=system.cpu_clk_domain,
size=options.v_size,assoc=options.v_assoc)
system.tovbus = L2XBar(clk_domain = system.cpu_clk_domain)
system.v.cpu_side = system.tovbus.master
system.v.mem_side = system.membus.slave
if options.memchecker:
system.memchecker = MemChecker()
for i in xrange(options.num_cpus):
if options.caches:
icache = icache_class(size=options.l1i_size,
assoc=options.l1i_assoc)
dcache = dcache_class(size=options.l1d_size,
assoc=options.l1d_assoc)
#Added L3 and VCache Options
if options.l3cache:
system.cpu[i].l2 = l2_cache_class(size=options.l2_size,
assoc=options.l2_assoc)
system.cpu[i].tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.cpu[i].l2.cpu_side = system.cpu[i].tol2bus.master
system.cpu[i].l2.mem_side = system.tol3bus.slave
if options.vcache:
system.cpu[i].l3 = l3_cache_class(size=options.l3_size,
assoc=options.l3_assoc)
system.cpu[i].tol3bus = L2XBar(clk_domain =
system.cpu_clk_domain)
system.cpu[i].l3.cpu_side = system.cpu[i].tol3bus.master
system.cpu[i].l3.mem_side = system.tovbus.slave
# If we have a walker cache specified, instantiate two
# instances here
if walk_cache_class:
iwalkcache = walk_cache_class()
dwalkcache = walk_cache_class()
else:
iwalkcache = None
dwalkcache = None
if options.memchecker:
dcache_mon = MemCheckerMonitor(warn_only=True)
dcache_real = dcache
# Do not pass the memchecker into the constructor of
# MemCheckerMonitor, as it would create a copy; we require
# exactly one MemChecker instance.
dcache_mon.memchecker = system.memchecker
# Connect monitor
dcache_mon.mem_side = dcache.cpu_side
# Let CPU connect to monitors
dcache = dcache_mon
# When connecting the caches, the clock is also inherited
# from the CPU in question
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
iwalkcache, dwalkcache)
if options.memchecker:
# The mem_side ports of the caches haven't been connected yet.
# Make sure connectAllPorts connects the right objects.
system.cpu[i].dcache = dcache_real
system.cpu[i].dcache_mon = dcache_mon
elif options.external_memory_system:
# These port names are presented to whatever 'external' system
# gem5 is connecting to. Its configuration will likely depend
# on these names. For simplicity, we would advise configuring
# it to use this naming scheme; if this isn't possible, change
# the names below.
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
system.cpu[i].addPrivateSplitL1Caches(
ExternalCache("cpu%d.icache" % i),
ExternalCache("cpu%d.dcache" % i),
ExternalCache("cpu%d.itb_walker_cache" % i),
ExternalCache("cpu%d.dtb_walker_cache" % i))
else:
system.cpu[i].addPrivateSplitL1Caches(
ExternalCache("cpu%d.icache" % i),
ExternalCache("cpu%d.dcache" % i))
system.cpu[i].createInterruptController()
#added this
if options.vcache:
system.cpu[i].connectAllPorts(system.cpu[i].tovbus, system.membus)
else:
if options.l3cache:
system.cpu[i].connectAllPorts(system.cpu[i].tol3bus,
system.membus)
#same as before
else:
if options.l2cache:
system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
else:
if options.external_memory_system:
system.cpu[i].connectUncachedPorts(system.membus)
else:
system.cpu[i].connectAllPorts(system.membus)
return system
# ExternalSlave provides a "port", but when that port connects to a cache,
# the connecting CPU SimObject wants to refer to its "cpu_side".
# The 'ExternalCache' class provides this adaptation by rewriting the name,
# eliminating distracting changes elsewhere in the config code.
class ExternalCache(ExternalSlave):
def __getattr__(cls, attr):
if (attr == "cpu_side"):
attr = "port"
return super(ExternalSlave, cls).__getattr__(attr)
def __setattr__(cls, attr, value):
if (attr == "cpu_side"):
attr = "port"
return super(ExternalSlave, cls).__setattr__(attr, value)
def ExternalCacheFactory(port_type):
def make(name):
return ExternalCache(port_data=name, port_type=port_type,
addr_ranges=[AllMemory])
return make
--END CacheConfig.Py--
--BEGIN Caches.py--
from m5.defines import buildEnv
from m5.objects import *
# Base implementations of L1, L2, IO and TLB-walker caches. There are
# used in the regressions and also as base components in the
# system-configuration scripts. The values are meant to serve as a
# starting point, and specific parameters can be overridden in the
# specific instantiations.
class L1Cache(Cache):
"""Simple L1 Cache with default values"""
# Default parameters for both L1 I and D caches
assoc = 2
tag_latency = 2
data_latency = 2
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
# is_top_level = True
def __init__(self, options=None):
super(L1Cache, self).__init__()
pass
def connectCPU(self, cpu_port):
""""Connect this cache's port to a CPU port"""
self.cpu_side = cpu_port
def connectBus(self, bus):
""""Connect this cache to a memory-side bus"""
self.mem_side = bus.slave
class L1_ICache(L1Cache):
"""Simple L1 instruction cache with default values"""
# Set the default size
size = '16kB'
def __init__(self, options=None):
super(L1_ICache, self).__init__()
pass
def connectCPU(self, cpu_port):
""""Connect this cache's port to a CPU port"""
self.cpu_side = cpu_port.icache_port
def connectBus(self, bus):
""""Connect this cache to a memory-side bus"""
self.mem_side = bus.slave
# super(L1ICache, self).__init__(options)
# if not options or not options.l1i_size:
# return
#self.size = options.l1i_size
class L1_DCache(L1Cache):
"""Simple L1 data cache with default values"""
# Set the default size
size = '64kB'
def __init__(self, options=None):
super(L1_DCache, self).__init__()
pass
def connectCPU(self, cpu_port):
""""Connect this cache's port to a CPU port"""
self.cpu_side = cpu_port.dcache_port
def connectBus(self, bus):
""""Connect this cache to a memory-side bus"""
self.mem_side = bus.slave
#super(L1DCache, self).__init__(options)
#if not options or not options.l1d_size:
# return
#self.size = options.l1d_size
class L2Cache(Cache):
"""Simple L2 Cache with default values"""
# Default parameters
size = '256kB'
assoc = 8
tag_latency = 6
data_latency = 6
response_latency = 6
mshrs = 20
tgts_per_mshr = 12
def __init__(self, options=None):
super(L2Cache, self).__init__()
pass
#super(L2Cache, self).__init__()
#if not options or not options.l2_size:
# return
#self.size = options.l2_size
def connectCPUSideBus(self, bus):
""""Connect this cache to a cpu-side bus"""
self.cpu_side = bus.master
def connectMemSideBus(self, bus):
""""Connect this cache to a memory-side bus"""
self.mem_side = bus.slave
#
# added L3 cache here
#
class L3Cache(Cache):
size = '2MB'
assoc = 16
tag_latency = 20
data_latency = 20
response_latency = 20
mshrs = 512
tgts_per_mshr = 20
write_buffers = 256
def __init__(self, options=None):
super(L3Cache, self).__init__()
pass
#super(L3Cache, self).__init__()
#if not options or not options.l2_size:
# return
#self.size = options.l2_size
def connectCPUSideBus(self, bus):
""""Connect this cache to a cpu-side bus"""
self.cpu_side = bus.master
def connectMemSideBus(self, bus):
""""Connect this cache to a memory-side bus"""
self.mem_side = bus.slave
class VCache(Cache):
size = '16kB'
assoc = 1
tag_latency = 2
data_latency = 2
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
write_buffers = 256
prefetcher = TaggedPrefetcher(degree=3)
tags = LRU()
def __init__(self, options=None):
super(VCache, self).__init__()
pass
#super(L3Cache, self).__init__()
#if not options or not options.l2_size:
# return
#self.size = options.l2_size
def connectCPUSideBus(self, bus):
""""Connect this cache to a cpu-side bus"""
self.cpu_side = bus.master
def connectMemSideBus(self, bus):
""""Connect this cache to a memory-side bus"""
self.mem_side = bus.slave
#prefetcher = 'tagged'
#
#
#
class IOCache(Cache):
assoc = 8
tag_latency = 50
data_latency = 50
response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
# here to
# forward_snoops = False
# is_top_level = True
#
class PageTableWalkerCache(Cache):
assoc = 2
tag_latency = 2
data_latency = 2
response_latency = 2
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
#
# added this line
#
# is_top_level = True
#
# the x86 table walker actually writes to the table-walker cache
if buildEnv['TARGET_ISA'] == 'x86':
is_read_only = False
else:
is_read_only = True
# Writeback clean lines as well
writeback_clean = True
--END Caches.py--
--BEGIN O3_ARM_v7a.py--
from m5.objects import *
# Simple ALU Instructions have a latency of 1
class O3_ARM_v7a_Simple_Int(FUDesc):
opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
count = 2
# Complex ALU instructions have a variable latencies
class O3_ARM_v7a_Complex_Int(FUDesc):
opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True),
OpDesc(opClass='IntDiv', opLat=12, pipelined=False),
OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
count = 1
# Floating point and SIMD instructions
class O3_ARM_v7a_FP(FUDesc):
opList = [ OpDesc(opClass='SimdAdd', opLat=4),
OpDesc(opClass='SimdAddAcc', opLat=4),
OpDesc(opClass='SimdAlu', opLat=4),
OpDesc(opClass='SimdCmp', opLat=4),
OpDesc(opClass='SimdCvt', opLat=3),
OpDesc(opClass='SimdMisc', opLat=3),
OpDesc(opClass='SimdMult',opLat=5),
OpDesc(opClass='SimdMultAcc',opLat=5),
OpDesc(opClass='SimdShift',opLat=3),
OpDesc(opClass='SimdShiftAcc', opLat=3),
OpDesc(opClass='SimdSqrt', opLat=9),
OpDesc(opClass='SimdFloatAdd',opLat=5),
OpDesc(opClass='SimdFloatAlu',opLat=5),
OpDesc(opClass='SimdFloatCmp', opLat=3),
OpDesc(opClass='SimdFloatCvt', opLat=3),
OpDesc(opClass='SimdFloatDiv', opLat=3),
OpDesc(opClass='SimdFloatMisc', opLat=3),
OpDesc(opClass='SimdFloatMult', opLat=3),
OpDesc(opClass='SimdFloatMultAcc',opLat=5),
OpDesc(opClass='SimdFloatSqrt', opLat=9),
OpDesc(opClass='FloatAdd', opLat=5),
OpDesc(opClass='FloatCmp', opLat=5),
OpDesc(opClass='FloatCvt', opLat=5),
OpDesc(opClass='FloatDiv', opLat=9, pipelined=False),
OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
OpDesc(opClass='FloatMult', opLat=4),
OpDesc(opClass='FloatMultAcc', opLat=5),
OpDesc(opClass='FloatMisc', opLat=3) ]
count = 2
# Load/Store Units
class O3_ARM_v7a_Load(FUDesc):
opList = [ OpDesc(opClass='MemRead',opLat=2),
OpDesc(opClass='FloatMemRead',opLat=2) ]
count = 1
class O3_ARM_v7a_Store(FUDesc):
opList = [ OpDesc(opClass='MemWrite',opLat=2),
OpDesc(opClass='FloatMemWrite',opLat=2) ]
count = 1
# Functional Units for this CPU
class O3_ARM_v7a_FUP(FUPool):
FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(),
O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()]
# Bi-Mode Branch Predictor
class O3_ARM_v7a_BP(BiModeBP):
globalPredictorSize = 8192
globalCtrBits = 2
choicePredictorSize = 8192
choiceCtrBits = 2
BTBEntries = 2048
BTBTagSize = 18
RASSize = 16
instShiftAmt = 2
class O3_ARM_v7a_3(DerivO3CPU):
LQEntries = 16
SQEntries = 16
LSQDepCheckShift = 0
LFSTSize = 1024
SSITSize = 1024
decodeToFetchDelay = 1
renameToFetchDelay = 1
iewToFetchDelay = 1
commitToFetchDelay = 1
renameToDecodeDelay = 1
iewToDecodeDelay = 1
commitToDecodeDelay = 1
iewToRenameDelay = 1
commitToRenameDelay = 1
commitToIEWDelay = 1
fetchWidth = 3
fetchBufferSize = 16
fetchToDecodeDelay = 3
decodeWidth = 3
decodeToRenameDelay = 2
renameWidth = 3
renameToIEWDelay = 1
issueToExecuteDelay = 1
dispatchWidth = 6
issueWidth = 8
wbWidth = 8
fuPool = O3_ARM_v7a_FUP()
iewToCommitDelay = 1
renameToROBDelay = 1
commitWidth = 8
squashWidth = 8
trapLatency = 13
backComSize = 5
forwardComSize = 5
numPhysIntRegs = 128
numPhysFloatRegs = 192
numIQEntries = 32
numROBEntries = 40
switched_out = False
branchPred = O3_ARM_v7a_BP()
# Instruction Cache
class O3_ARM_v7a_ICache(Cache):
tag_latency = 1
data_latency = 1
response_latency = 1
mshrs = 2
tgts_per_mshr = 8
size = '16kB'
assoc = 2
is_read_only = True
# Writeback clean lines as well
writeback_clean = True
# Data Cache
class O3_ARM_v7a_DCache(Cache):
tag_latency = 2
data_latency = 2
response_latency = 2
mshrs = 6
tgts_per_mshr = 8
size = '64kB'
assoc = 2
write_buffers = 16
# Consider the L2 a victim cache also for clean lines
writeback_clean = True
# TLB Cache
# Use a cache as a L2 TLB
class O3_ARM_v7aWalkCache(Cache):
tag_latency = 4
data_latency = 4
response_latency = 4
mshrs = 6
tgts_per_mshr = 8
size = '1kB'
assoc = 8
write_buffers = 16
is_read_only = True
# Writeback clean lines as well
writeback_clean = True
# L2 Cache
class O3_ARM_v7aL2(Cache):
tag_latency = 12
data_latency = 12
response_latency = 12
mshrs = 16
tgts_per_mshr = 8
size = '256kB'
assoc = 16
write_buffers = 8
prefetch_on_access = True
clusivity = 'mostly_excl'
# L2 Cache
class O3_ARM_v7aL3(Cache):
tag_latency = 20
data_latency = 20
response_latency = 20
mshrs = 512
tgts_per_mshr = 20
size = '2MB'
assoc = 16
write_buffers = 256
prefetch_on_access = True
clusivity = 'mostly_excl'
# L2 Cache
class O3_ARM_v7aV(Cache):
tag_latency = 2
data_latency = 2
response_latency = 2
mshrs = 6
tgts_per_mshr = 20
size = '16kB'
assoc = 1
write_buffers = 256
# Consider the L2 a victim cache also for clean lines
writeback_clean = True
prefetcher = TaggedPrefetcher(degree=3)
tags = LRU()
--END O3_ARM_v7a.py--
Thank you all for your help.
-Brian Suchy
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
