Hi, It's unfortunately not that simple to extend the fs.py script. It uses complex and inflexible logic to set up the system. I would strongly encourage you to write your own script from scratch to support this. You can find an example for X86 here: http://learning.gem5.org/book/part3/index.html.
Of course, this script won't work for ARM, but it does show an example of how things can work. You should be able to copy code out of configs/common/ and put it in your System object to get full system support for ARM. There is a *huge* upside for writing your own scripts, other than just having added flexibility. By writing your own scripts you are required to fully understand how everything works. This makes it much less likely for you to model something incorrectly (accidentally) since you must understand everything that you're using. Hopefully this will get you started. I would like to add a simple_fs for ARM, but I haven't had the time to do it. Maybe later this semester or this summer I'll find the time. Cheers, Jason On Thu, Feb 2, 2017 at 5:32 AM Adamo, Anthony M <[email protected]> wrote: Hello everyone, I have created a cache hierarchy that I would like to use for my FS mode emulation for the Asim benchmark. The hierarchy is based upon the Two-Level Cache Hierarchy in the tutorials, but with an added L3 cache and Victim Cache (will be pasting the code below). Originally to make the cache, I used the (modified to accommodate the new caches) two_level.py script (located in /configs/learning_gem5/part1) that would be used in the command prompt line : build/ARM/gem5.opt configs/learning_gem5/part1/two_level.py But because I am not using the two_level.py anymore I need to figure out how to integrate my new cache hierarchy into the FS.py file. The command that I am currently using is as follows: build/ARM/gem5.opt configs/example/fs.py --kernel=/asimBenchmark/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35 --dtb-file=/asimBenchmark/binaries/vexpress-v2p-ca15-tc1.dtb --disk-image=/asimBenchmark/disks/ARMv7a-ICS-Android.SMP.Asimbench-v3.img --script=/asimBenchmark/scripts/*Insert the script I will use* --os-type=android-ics --mem-size=256MB --machine-type=RealView_PBX So the primary question that needs to be answered is how to go about making my new cache hierarchy used in the fs simulation. Another question is if I should be modifying the above command prompt line at all to accommodate my cache hierarchy. Finally, assuming it gets added and all is well, will the m5out folder (on the host machine) still hold the stats.txt file for the benchmark I run? Thank you all for your help. Here are the modified files: BEGIN THE TWO-LEVEL FILE two_level.py: import m5 # import all of the SimObjects from m5.objects import * # Add the common scripts to our path m5.util.addToPath('../') # import the caches which we made from caches import * # import the SimpleOpts module from family_common import SimpleOpts # Set the usage message to display SimpleOpts.set_usage("usage: %prog [options] <binary to execute>") # Finalize the arguments and grab the opts so we can pass it on to our objects (opts, args) = SimpleOpts.parse_args() # get ISA for the default binary to run. This is mostly for simple testing isa = "x86" # Default to running 'hello', use the compiled ISA to find the binary binary = 'tests/test-progs/hello/bin/' + isa + '/Benchmarks/SplashII/ocean/ocean.i386' # Check if there was a binary passed in via the command line and error if # there are too many arguments if len(args) == 1: binary = args[0] elif len(args) > 1: SimpleOpts.print_help() m5.fatal("Expected a binary to execute as positional argument") # create the system we are going to simulate system = System() # Set the clock fequency of the system (and all of its children) system.clk_domain = SrcClockDomain() system.clk_domain.clock = '1GHz' system.clk_domain.voltage_domain = VoltageDomain() # Set up the system system.mem_mode = 'timing' # Use timing accesses system.mem_ranges = [AddrRange('512MB')] # Create an address range # Create a simple CPU system.cpu = TimingSimpleCPU() # Create an L1 instruction and data cache system.cpu.icache = L1ICache(opts) system.cpu.dcache = L1DCache(opts) # Connect the instruction and data caches to the CPU system.cpu.icache.connectCPU(system.cpu) system.cpu.dcache.connectCPU(system.cpu) # Create a memory bus system.membus = SystemXBar() # Create a memory bus, a coherent crossbar, in this case system.l2bus = L2XBar() # Create a memory bus, a coherent crossbar, in this case system.l3bus = L2XBar() system.vbus = L2XBar() # Hook the CPU ports up to the l2bus system.cpu.icache.connectBus(system.l2bus) system.cpu.dcache.connectBus(system.l2bus) # Hook the CPU ports up to the l3bus #system.cpu.icache.connectBus(system.l3bus) #system.cpu.dcache.connectBus(system.l3bus) # Create an L2 cache and connect it to the l2bus system.l2cache = L2Cache(opts) system.l2cache.connectCPUSideBus(system.l2bus) # Connect the L2 cache to the membus system.l2cache.connectMemSideBus(system.l3bus) # Create an L3 cache and connect it to the l3bus system.l3cache = L3Cache(opts) system.l3cache.connectCPUSideBus(system.l3bus) # Connect the L2 cache to the membus system.l3cache.connectMemSideBus(system.vbus) system.vcache = VCache(opts) system.vcache.connectCPUSideBus(system.vbus) system.vcache.prefetch_on_access = 'true' system.vcache.prefetcher = TaggedPrefetcher(degree = 3) # Connect the L2 cache to the membus system.vcache.connectMemSideBus(system.membus) # create the interrupt controller for the CPU system.cpu.createInterruptController() # For x86 only, make sure the interrupts are connected to the memory # Note: these are directly connected to the memory bus and are not cached if m5.defines.buildEnv['TARGET_ISA'] == "x86": system.cpu.interrupts[0].pio = system.membus.master system.cpu.interrupts[0].int_master = system.membus.slave system.cpu.interrupts[0].int_slave = system.membus.master # Connect the system up to the membus system.system_port = system.membus.slave # Create a DDR3 memory controller system.mem_ctrl = DDR3_1600_x64() system.mem_ctrl.range = system.mem_ranges[0] system.mem_ctrl.port = system.membus.master # Create a process for a simple "Hello World" application process = LiveProcess() # Set the command # Run 'hello' and use the compiled ISA to find the binary #binary = 'tests/test-progs/hello/bin/x86/linux/hello' # cmd is a list which begins with the executable (like argv) process.cmd = [binary] # Set the cpu to use the process as its workload and create thread contexts system.cpu.workload = process system.cpu.createThreads() # set up the root SimObject and start the simulation root = Root(full_system = False, system = system) # instantiate all of the objects we've created above m5.instantiate() print "Beginning simulation!" exit_event = m5.simulate() print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()) END FILE BEGIN THE CACHE FILE: caches.py: # Copyright (c) 2012 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall # not be construed as granting a license to any other intellectual # property including but not limited to intellectual property relating # to a hardware implementation of the functionality of the software # licensed hereunder. You may use the software subject to the license # terms below provided that you ensure that this notice is replicated # unmodified and in its entirety in all distributions of the software, # modified or unmodified, in source code or in binary form. # # Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are # met: redistributions of source code must retain the above copyright # notice, this list of conditions and the following disclaimer; # redistributions in binary form must reproduce the above copyright # notice, this list of conditions and the following disclaimer in the # documentation and/or other materials provided with the distribution; # neither the name of the copyright holders nor the names of its # contributors may be used to endorse or promote products derived from # this software without specific prior written permission. # # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Lisa Hsu from m5.defines import buildEnv from m5.objects import * # Base implementations of L1, L2, IO and TLB-walker caches. There are # used in the regressions and also as base components in the # system-configuration scripts. The values are meant to serve as a # starting point, and specific parameters can be overridden in the # specific instantiations. class L1Cache(Cache): assoc = 2 tag_latency = 2 data_latency = 2 response_latency = 2 mshrs = 4 tgts_per_mshr = 20 # added this # is_top_level = True # # class L1_ICache(L1Cache): is_read_only = True # Writeback clean lines as well writeback_clean = True class L1_DCache(L1Cache): pass class L2Cache(Cache): assoc = 8 tag_latency = 8 data_latency = 20 response_latency = 20 mshrs = 20 tgts_per_mshr = 16 write_buffers = 8 # # added L3 cache here # class L3Cache(Cache): assoc = 16 hit_latency = 20 response_latency = 20 mshrs = 512 tgts_per_mshr = 20 write_buffers = 256 class VCache(Cache): assoc = 1 hit_latency = 2 response_latency = 2 mshrs = 20 tgts_per_mshr = 20 write_buffers = 8 # # # class IOCache(Cache): assoc = 8 tag_latency = 50 data_latency = 50 response_latency = 50 mshrs = 20 size = '1kB' tgts_per_mshr = 12 # here to forward_snoops = False is_top_level = True # class PageTableWalkerCache(Cache): assoc = 2 tag_latency = 2 data_latency = 2 response_latency = 2 mshrs = 10 size = '1kB' tgts_per_mshr = 12 # # added this line # is_top_level = True # # the x86 table walker actually writes to the table-walker cache if buildEnv['TARGET_ISA'] == 'x86': is_read_only = False else: is_read_only = True # Writeback clean lines as well writeback_clean = True END FILE Thank you again for all your help. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
