Hello, The program src/arch/isa_parser.py is supposed to translate .isa files to generated .cc/.hh ones. Try to grep your instructions in build/ARM/arch/arm/generated/decoder-ns.*.inc, so you can see the generated files where _destRegIdx and _srcRegIdx are filled.
Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2016-12-15 11:41 GMT+01:00 Will <[email protected]>: > Hello, > > I am doing some instruction dependency check related work using the > decoder and static inst. in gem5 (built for ARM). > However, I found that for some instructions, the member `_destRegIdx` and > `_srcRegIdx` in `class StaticInst` can't give the right destination and > source registers. For example, > > 13900: e49d5004 pop {r5} ; (ldr r5, [sp], #4) > // From objdump > _destRegIdx = {0, 0, 0, 0, 0, 0, 0, 0}, > // From (gdb) p *curStaticInst > _srcRegIdx = {0 <repeats 34 times>}, > > 14554: e5843000 str r3, [r4] > // From objdump > _destRegIdx = {0, 0, 0, 0, 0, 0, 0, 0}, > // From (gdb) p *curStaticInst > _srcRegIdx = {4, 1542, 1541, 1541, 1541, 3, 0 <repeats 28 times>}, > > 14584: e8bd0ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp} > // From objdump > _destRegIdx = {0, 0, 0, 0, 0, 0, 0, 0}, > _srcRegIdx = {0 <repeats 34 times>}, > > Did I used the wrong function to get the source and destination registers? > Or there is any easier way to do dependency check using gem5? > Your help is greatly appreciated. > > Wil > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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