Dear all,

I ran a full system simulation with four cores CPU, in which each core is 
hardcoded (using taskset command) to run a specific SPEC CPU2006 benchmarks 
(leslie3d, leslie3d, mcf, and mcf). The architecture of the simulated system 
can be inferred from the simulation command below:

build/X86/gem5.fast configs/example/fs.py --caches 
--disk-image=linux-x86-large.img --kernel=x86_64-vmlinux-3.2.24.smp 
--l1d_size=128kB --l1i_size=128kB --l2cache --l2_size=8MB --l2_assoc=8 
--cacheline_size=64 -n 4 --mem-size=8GB --cpu-clock=4GHz --sys-clock=4GHz 
--mem-type=DDR3_1600_x64 --cpu-type=detailed -r 2 -I 250000000

Here is the result of the number of instructions and number of cycles simulated 
for each core:

system.switch_cpus0.commit.committedInsts       276150                       # 
Number of instructions committed
system.switch_cpus1.commit.committedInsts    250000000                       # 
Number of instructions committed
system.switch_cpus2.commit.committedInsts      8546307                       # 
Number of instructions committed
system.switch_cpus3.commit.committedInsts     35930361                       # 
Number of instructions committed

system.switch_cpus0.numCycles                  864447                       # 
number of cpu cycles simulated
system.switch_cpus1.numCycles                63273161                       # 
number of cpu cycles simulated
system.switch_cpus2.numCycles                 6382626                       # 
number of cpu cycles simulated
system.switch_cpus3.numCycles                26166842                       # 
number of cpu cycles simulated


I can understand a small variation in the number of cycles/instructions between 
the cores; however, the variation in this case is huge. For example, why would 
the second core run faster than the first, even though they are running the 
same benchmark (leslie3d) with the same exact input (reference input)? In fact, 
the first core has an IPC of 0.32, while the second has an IPC of 3.95 (more 
that 10x faster).

Also, is there a way to make the simulation fair, in the sense that each core 
is simulated for approximately the same number of cycles (or the same number of 
instructions)?

Thank you,
Ali.
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