Is there anything in m5out/*terminal*? I would bet that something is going wrong early in the boot process and gem5 is not booting the OS correctly.
Jason On Mon, Feb 13, 2017 at 10:51 AM SHARJEEL KHILJI < [email protected]> wrote: > Hi > > I am finally able to run the ARM+ RUBY full system. But there is a problem > the m5 terminal is attached with the simulation but nothing appears in the > terminal. > > ./build/ARM/gem5.fast configs/example/fs.py --l2cache --cacheline_size=64 > --l1d_size=32kB --l1i_size=32kB --l2_size=1MB > --machine-type=VExpress_GEM5_V1 --kernel > /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image > /home/khilji/gem5/m5/system/disks/aarch64-ubuntu-trusty-headless.img > --dtb-filename /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_4cpu.dtb > --num-cpus=4 --cpu-type=timing --mem-size=512MB --ruby --num-dirs=2 > --garnet-network flexible --topology Mesh --mesh-rows 2 --numa-high-bit=28 > gem5 Simulator System. http://gem5.org > gem5 is copyrighted software; use the --copyright option for details. > > gem5 compiled Feb 13 2017 12:34:48 > gem5 started Feb 13 2017 21:34:17 > gem5 executing on ubuntu-machine, pid 3862 > command line: ./build/ARM/gem5.fast configs/example/fs.py --l2cache > --cacheline_size=64 --l1d_size=32kB --l1i_size=32kB --l2_size=1MB > --machine-type=VExpress_GEM5_V1 --kernel > /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image > /home/khilji/gem5/m5/system/disks/aarch64-ubuntu-trusty-headless.img > --dtb-filename /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_4cpu.dtb > --num-cpus=4 --cpu-type=timing --mem-size=512MB --ruby --num-dirs=2 > --garnet-network flexible --topology Mesh --mesh-rows 2 --numa-high-bit=28 > > > Global frequency set at 1000000000000 ticks per second > warn: DRAM device capacity (8192 Mbytes) does not match the address range > assigned (256 Mbytes) > warn: DRAM device capacity (8192 Mbytes) does not match the address range > assigned (256 Mbytes) > > info: kernel located at: > /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 > Listening for system connection on port 5900 > Listening for system connection on port 3456 > 0: system.remote_gdb.listener: listening for remote gdb on port 7000 > 0: system.remote_gdb.listener: listening for remote gdb on port 7001 > 0: system.remote_gdb.listener: listening for remote gdb on port 7002 > 0: system.remote_gdb.listener: listening for remote gdb on port 7003 > warn: ClockedObject: More than one power state change request encountered > within the same simulation tick > warn: ClockedObject: More than one power state change request encountered > within the same simulation tick > warn: ClockedObject: More than one power state change request encountered > within the same simulation tick > warn: ClockedObject: More than one power state change request encountered > within the same simulation tick > info: Using bootloader at address 0x10 > info: Using kernel entry physical address at 0x80008000 > info: Loading DTB file: > /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_4cpu.dtb at address 0x88000000 > > **** REAL SIMULATION **** > warn: Existing EnergyCtrl, but no enabled DVFSHandler found. > info: Entering event queue @ 0. Starting simulation... > warn: Replacement policy updates recently became the responsibility of > SLICC state machines. Make sure to setMRU() near callbacks in .sm files! > warn: The csselr register isn't implemented. > warn: The ccsidr register isn't implemented and always reads as 0. > warn: instruction 'mcr dcisw' unimplemented > warn: Not doing anything for miscreg ACTLR > warn: Not doing anything for write of miscreg ACTLR > warn: instruction 'mcr dccmvau' unimplemented > warn: instruction 'mcr icimvau' unimplemented > warn: instruction 'mcr bpiallis' unimplemented > warn: The clidr register always reports 0 caches. > warn: clidr LoUIS field of 0b001 to match current ARM implementations. > warn: instruction 'mcr icialluis' unimplemented > warn: instruction 'mcr dccimvac' unimplemented > info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 > info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 > info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 > info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 > info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 > info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 > info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 > warn: Not doing anything for miscreg ACTLR > warn: Not doing anything for write of miscreg ACTLR > warn: instruction 'mcr bpiall' unimplemented > warn: Not doing anything for miscreg ACTLR > warn: Not doing anything for write of miscreg ACTLR > warn: Not doing anything for miscreg ACTLR > warn: Not doing anything for write of miscreg ACTLR > warn: Tried to read RealView I/O at offset 0x60 that doesn't exist > warn: Tried to read RealView I/O at offset 0x48 that doesn't exist > > telnet 127.0.0.1 3456 > Trying 127.0.0.1... > Connected to 127.0.0.1. > Escape character is '^]'. > ==== m5 slave terminal: Terminal 0 ==== > But nothing appears after this. Kindly, if someone can guide me in this > regard. > > best regards, > Sharjeel > > > > On 11 February 2017 at 15:48, SHARJEEL KHILJI < > [email protected]> wrote: > > Hi, > sorry it was 512MB the mem-size = 512 MB in build commands. > > best regards, > > Sharjeel > > > On 11 February 2017 at 15:33, SHARJEEL KHILJI < > [email protected]> wrote: > > HI, > Thanks for your help, I have tried to figure out where is that > uninitialized stat. Actually the assertion fails in safe_cast function in > cast.hh which is further called in prepare() in Statistics.h. I can not > figure out where is the list of all stats is populated and where is > prepare() is called in all repository which can help to trace that > uninitialized stat. > May be the following error will help > > **** REAL SIMULATION **** > warn: Existing EnergyCtrl, but no enabled DVFSHandler found. > gem5.debug: build/ARM/base/cast.hh:49: T safe_cast(U) [with T = const > Stats::DistStor::Params*; U = const Stats::StorageParams*]: Assertion `ret' > failed. > Program aborted at tick 0 > Build commands are > > scons build/ARM/gem5.debug PROTOCOL=MI_example -j2 > ./build/ARM/gem5.debug --debug-flags=Exec,ExecTicks > configs/example/fs.py --machine-type=VExpress_GEM5_V1 --kernel > /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image > /home/khilji/gem5/m5/system/disks/linux-aarch32-ael.img --dtb-filename > /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_4cpu.dtb --num-cpus=4 > --cpu-type=timing --mem-size=1MB --ruby --num-dirs=1 --garnet-network > flexible --topology Mesh --mesh-rows 2 > > best regards, > Sharjeel > > > > On 6 February 2017 at 00:44, Jason Lowe-Power <[email protected]> wrote: > > Hi Sharjeel, > > Have you changed any code? Usually, this problem is "*You may need to add > <ParentClass>::regStats() to a new SimObject's regStats() function." *If > you've added a regStats function somewhere, that's probably the issue. If > you've just changed/added a stat, it could be that the stat isn't > registered in regStats(). > > If you haven't changed the code at all... I'm surprised that this is in > the mainline. Let me know if you haven't made any changes and we can try to > work out what stat isn't being initialized. > > Cheers, > Jason > > On Sun, Feb 5, 2017 at 8:55 AM SHARJEEL KHILJI < > [email protected]> wrote: > > Hi, > Thanks for helping me with the directory and memory controller connection > issue. > Kindly, if you can guide me about the following issue. Note: MI_example is > sized to cover all physical memory range > > scons build/ARM/gem5.debug PROTOCOL=MI_example -j2 > ./build/ARM/gem5.debug --debug-flags=Exec,ExecTicks > configs/example/fs.py --machine-type=VExpress_GEM5_V1 --kernel > /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image > /home/khilji/gem5/m5/system/disks/linux-aarch32-ael.img --dtb-filename > /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_4cpu.dtb --num-cpus=4 > --cpu-type=timing --mem-size=1GB --ruby --num-dirs=1 --garnet-network > flexible --topology Mesh --mesh-rows 2 > > gem5 compiled Feb 5 2017 16:56:37 > gem5 started Feb 5 2017 19:31:30 > gem5 executing on ubuntu-machine, pid 8428 > command line: ./build/ARM/gem5.debug --debug-flags=Exec,ExecTicks > configs/example/fs.py --machine-type=VExpress_GEM5_V1 --kernel > /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image > /home/khilji/gem5/m5/system/disks/linux-aarch32-ael.img --dtb-filename > /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_4cpu.dtb --num-cpus=4 > --cpu-type=timing --mem-size=1GB --ruby --num-dirs=1 --garnet-network > flexible --topology Mesh --mesh-rows 2 > > Global frequency set at 1000000000000 ticks per second > warn: DRAM device capacity (8192 Mbytes) does not match the address range > assigned (1024 Mbytes) > info: kernel located at: > /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 > Listening for system connection on port 5900 > Listening for system connection on port 3456 > 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 > 0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001 > 0: system.remote_gdb.listener: listening for remote gdb #2 on port 7002 > 0: system.remote_gdb.listener: listening for remote gdb #3 on port 7003 > > > > *this is stat number 1299panic: Not all stats have been initialized.You > may need to add <ParentClass>::regStats() to a new SimObject's regStats() > function. @ tick 0* > [baseCheck:build/ARM/base/statistics.cc, line 226] > Memory Usage: 1771200 KBytes > Program aborted at tick 0 > --- BEGIN LIBC BACKTRACE --- > > best regards, > Sharjeel > > > On 4 February 2017 at 21:34, Jason Lowe-Power <[email protected]> wrote: > > Hi Sharjeel, > > This function is only called from other places in the configs directory. I > would trace back where this function is called from to find what dir_cntrls > is. IIRC, it's created in the protocol-specific python files. > > Cheers, > Jason > > On Sat, Feb 4, 2017 at 6:06 AM SHARJEEL KHILJI < > [email protected]> wrote: > > Hi, > Thanks for your reply that helped me a lot. Kindly, if you can tell me > that where in /src can I find the definition of dir_cntrls a list of > directory controllers. This is used in setup_memory_controllers function in > ruby.py > def setup_memory_controllers(system, ruby, dir_cntrls, options): > > best regards, > Sharjeel > > > On 24 January 2017 at 20:41, Jason Lowe-Power <[email protected]> wrote: > > Hello, > > Ruby is known to have issues when using the ARM ISA. It's likely a problem > with how the system is configured. I would strongly encourage you to not > use fs.py, but to write a new Python configuration script from scratch if > you need to do unsupported things like ARM + Ruby. Another option is to use > Ruby + x86, which is better supported. > > As a side note, the option --caches enables the classic caches and --ruby > enables Ruby, you should choose only one of them. Additionally, the command > line options for cache sizes may or may not work with Ruby depending on the > coherence protocol. > > Cheers, > Jason > > On Tue, Jan 24, 2017 at 5:01 AM SHARJEEL KHILJI < > [email protected]> wrote: > > > Hi, i am trying to simulate full system NOC (ARM system) with ruby memory > system and i get following error. I am trying to use different topologies > to resolve the following error. > Kindly, if some one can guide me in this regard. > > scons build/ARM/gem5.fast PROTOCOL=MI_example -j2 > > ./build/ARM/gem5.fast configs/example/fs.py --caches --cacheline_size=64 > --l1d_size=32kB --l1i_size=32kB --l2_size=1MB > --machine-type=VExpress_GEM5_V1 --kernel > /home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image > /home/khilji/gem5/m5/system/disks/linux-aarch32-ael.img --dtb-filename > /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_4cpu.dtb --num-cpus=4 > --cpu-type=timing --mem-size=128MB --numa-high-bit=128 --ruby --num-dirs=4 > --garnet-network=flexible --topology=Mesh --mesh-rows=2 > > fatal: Port <orphan LinuxArmSystem>.ruby.dir_cntrl0.memory is already > connected to <orphan DDR3_1600_x64>.port, cannot connect <orphan > DDR3_1600_x64>.port. > > best regards, > > Muhammad Sharjeel Khilji > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > -- > > Jason > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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