Hi Subhankar, You can increase the width of the crossbar. Though, I believe after 64B increasing the width does not make a difference. You could also increase the clock rate of the crossbar (e.g., 2X the cache clock) to simulate a multi-ported crossbar. Finally, you could add a new crossbar model, or modify the current crossbar to support multiple ports.
For simulating multiple main-memory channels, you can instantiate multiple DRAM controllers and assign each controller a memory range (AddrRange). These ranges can be interleaved, too. See configs/common/MemConfig.py for an example. Jason On Mon, Feb 13, 2017 at 10:56 PM Subhankar Pal <[email protected]> wrote: > Hi all, > > I am trying to build a hierarchy of caches and tester CPUs using memtest > (configs/examples/memtest.py) as my reference. I am able to connect regular > XBars and caches normally, but I want an *N*-ported connection between a > cache and a XBar (i.e. *N* simultaneous requests should be able to go > from XBar to cache and vice versa). How do I achieve this? Also, I would > like to know how to simulate multiple channels in the main memory. > > Any pointers/explanation is highly appreciated. Thanks in advance for your > help! > > Subhankar Pal > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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