Hello, Number of cache ports is supposed to limit the number of store writes to the L1D cache. Maybe you need a wide pipe to notice any change of this param. I'd suggest varying it between 1 and 4 depending on the aggressiveness of your configuration.
Regards, -- Fernando A. Endo, Post-doc INRIA Rennes-Bretagne Atlantique France 2017-02-22 18:25 GMT+01:00 yuhang liu <[email protected]>: > Hi All, > > It is found that two parameters of GEM5 do not take effect. > > One parameter is "number of cache ports", and the other is " the number of > targets per MSHR" of L2 cache. For the latter parameter, it is found that " > the number of targets per MSHR" of L1 i/d cache take effect. > > Could someone can validate and explain this fact? > > Many thanks. > > John > > > > > > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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