Hi, It does have data: (not the dram_ctrl.cc, but abstract_mem.cc) So, the way it works is: data is loaded into the memory space (pmemAddr), which actually stores data. DRAMSim etc as you pointed out gives a wrapper to simulate DRAM accesses, but the packet when it needs data is finally loaded from abstract_mem.cc. Cache in gem5 does handle data and it gets it from this particular memory. I have checked the flow and also am able to see the data flow.
My question is: How do I load the data completely before access happens. >From what I understand, data gets loaded only when accessed for the first time (they seem to be doing it using functional access or something like that) In dram_ctrl.cc: // do the actual memory access and turn the packet into a response access(pkt); In abstract_mem.cc: (In the access function) uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start(); std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); On Wed, Mar 22, 2017 at 12:48 PM, hassan yamin <[email protected]> wrote: > From my observation, if you see the AbstractMemory.py file, there is a > parameter null, which states that do not store data, always return > zero.. I have debugged it in DRAMSim2, it actually returns no data... > Check this again.. > > On Wed, Mar 22, 2017 at 1:39 PM, Navin Kashyap > <[email protected]> wrote: > > Hi, > > Yes, the data is stored in abstract_mem.cc as physical memory. So, when > the > > page is first touched, I access all the addresses that belong to the page > > from abstract_mem (physical memory), to collect the stats. But I see that > > the entire data is not loaded for the range of addresses in the page. > > > > On Wed, Mar 22, 2017 at 12:36 PM, hassan yamin <[email protected] > > > > wrote: > >> > >> Navin, i think u are missing something, the dram_ctrl.cc or or any > >> other dram simulator like DRAMSim2 does not do any actual data > >> storage. They just simulate the DRAM for performance and energy > >> consumption related stats. They are not meant to do any actual data > >> storage. Hope that helps. > >> > >> Hassan > >> > >> On Wed, Mar 22, 2017 at 1:19 PM, Navin Kashyap > >> <[email protected]> wrote: > >> > Hi, > >> > I am running gem5 in SE mode with DRAM. > >> > I wanted to collect stats per page (row) in the main memory (DRAM). > >> > I have added code such that when a page is first accessed, I visit all > >> > the > >> > columns and collect the stats related to the data each column holds. > >> > But, I think that the entire page (row) is not loaded when the page is > >> > first > >> > accessed (apart from writing to abstract memory from dram_ctrl.cc, > there > >> > are > >> > other paths to write data)? > >> > How do I know when the entire page is loaded in SE mode? > >> > > >> > I am using 8kB row size. > >> > > >> > Thanks, > >> > Navin > >> > > >> > _______________________________________________ > >> > gem5-users mailing list > >> > [email protected] > >> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > >> _______________________________________________ > >> gem5-users mailing list > >> [email protected] > >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > > > > > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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