Yes, you are correct. It is 62.2%. The statistics you referenced are ratios.
Jason On Sat, May 13, 2017 at 12:07 PM Moussa, Ayman < [email protected]> wrote: > I'm looking into stats.txt for lines regarding the overall miss rates for > L1 I and D-caches/L2 caches but there are too many ambiguous lines, for > example > > > system.cpu.dcache.ReadReq_miss_rate::total > 0.091585 # miss rate for ReadReq accesses > system.cpu.dcache.WriteReq_miss_rate::cpu.data > 0.182552 # miss rate for WriteReq accesses > system.cpu.dcache.WriteReq_miss_rate::total > 0.182552 # miss rate for WriteReq accesses > system.cpu.dcache.demand_miss_rate::cpu.data > 0.116630 # miss rate for demand accesses > system.cpu.dcache.demand_miss_rate::total > 0.116630 # miss rate for demand accesses > system.cpu.dcache.overall_miss_rate::cpu.data > 0.116630 # miss rate for overall accesses > system.cpu.dcache.overall_miss_rate::total > 0.116630 # miss rate for overall accesses > > > Why are some of these results the same? Am I right in concluding that the > following: > > > system.cpu.dcache.overall_miss_rate::total 0.116630 > > system.cpu.icache.overall_miss_rate::total > 0.000091 # miss rate for overall accesses > > system.l2.overall_miss_rate::total > 0.622004 # miss rate for overall accesses > > > Represent the overall miss rate for the L1 D-Cache, L1 I-Cache and L2 > cache respectively? Also, is the miss rate for the L2 cache above 0.62% or > 62.2%? > > > Help much appreciated > > Thanks > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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