Hi Kleovoulos,
Thank you for your reply. I was able to identify NEON instruction data-widths
using the same logic that you described. Describing it below for future
reference -
VADD instruction is as described below:
VADD{cond}.datatype {Qd}, Qn, Qm ----> where datatype is I8, I16, I32, or I64.
>From "src/arch/arm/isa/insts/neon.isa", I find that this instruction is
>implemented as NVaddD.
And this can be found in "./build/ARM/arch/arm/generated/exec-ns.cc.inc" as
show below:
"
template
Fault NVaddD<uint8_t>::execute(
CPU_EXEC_CONTEXT *, Trace::InstRecord *) const;
template
Fault NVaddD<uint16_t>::execute(
CPU_EXEC_CONTEXT *, Trace::InstRecord *) const;
template
Fault NVaddD<uint32_t>::execute(
CPU_EXEC_CONTEXT *, Trace::InstRecord *) const;
template
Fault NVaddD<uint64_t>::execute(
CPU_EXEC_CONTEXT *, Trace::InstRecord *) const;
"
>From above, the possible data-widths are 8-bit to 64-bit.
I dynamically identify the width for the executing instruction by simply
reading the size of "Element" in the below code:
"
Fault NVaddD<Element>::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
.
.
.
DPRINTF(Arm,"%d\n",sizeof(Element));
.
.
}
"
Thank you for your inputs!
- Gokul
________________________________
From: gem5-users <[email protected]> on behalf of
[email protected] <[email protected]>
Sent: Monday, June 12, 2017 11:00 AM
To: [email protected]
Subject: gem5-users Digest, Vol 131, Issue 10
Send gem5-users mailing list submissions to
[email protected]
To subscribe or unsubscribe via the World Wide Web, visit
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
or, via email, send a message with subject or body 'help' to
[email protected]
You can reach the person managing the list at
[email protected]
When replying, please edit your Subject line so it is more specific
than "Re: Contents of gem5-users digest..."
Today's Topics:
1. Invalid transition DMA controller in NoC (SHARJEEL KHILJI)
2. Re: Invalid transition DMA controller in NoC (Nikos Nikoleris)
3. Re: Datatype (data-width) of NEON operations for ARM in Gem5
(Kleovoulos Kalaitzidis)
4. Re: BBV file not generated(or found) (Oscar Rosell)
5. Re: SystemC and GEM5 SE Mode (Qureshi Yasir Mahmood)
6. Memory Mapping SE - Virtual to Physical Address
(Qureshi Yasir Mahmood)
----------------------------------------------------------------------
Message: 1
Date: Mon, 12 Jun 2017 11:56:51 +0500
From: SHARJEEL KHILJI <[email protected]>
To: gem5 users mailing list <[email protected]>
Subject: [gem5-users] Invalid transition DMA controller in NoC
Message-ID:
<caemrrtz4m06apd5jfimhzam3xlpdikxn5ngesf1ham06jf6...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi,
I am running the following system,
scons build/ARM/gem5.debug PROTOCOL=MESI_Two_Level
./build/ARM/gem5.debug --debug-flags ProtocolTrace configs/example/fs.py
--l1d_size=32kB --l1i_size=32kB --num-l2caches 4 --l2_size=1MB
--cacheline_size=64 --machine-type=VExpress_GEM5_V1 --kernel
/home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image
/home/khilji/gem5/m5/system/disks/arm-ubuntu-natty-headless.img
--dtb-filename /home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_4cpu.dtb
--num-cpus=4 --ruby --num-dirs=4 --network=garnet2.0 --topology Mesh_XY
--mesh-rows 2 --mem-size 1GB --cpu-clock 1GHz
While running this in debug, and booting the linux I get the following
invalid DMA transition.
When DMA controller receives the read request from the DMA sequencer it
moves to the busy read state
but when input response (Data) is received from (Directory/or PUTX L1) the
DMA has already returned to
ready state before Data event occurs. There are three DMA controllers
(equal to dma ports) in the system as specified in config.ini.
Is this because of the fact that one of the controllers issues the read
request to directory and all of the controllers receive the response?
and then those who have not issued the request receive the response while
in ready state which results in exception.
Following is the protocol trace
646885666000 2 L1Cache Load
M>M [0xbda99a00, line 0xbda99a00]
646885667000 2 Seq Begin
> [0x80359d7c, line 0x80359d40] IFETCH
646885668000 2 Seq Done
> [0x80359d7c, line 0x80359d40] 1 cycles
646885668000 2 L1Cache Ifetch
S>S [0x80359d40, line 0x80359d40]
646885670500 1 DMA ReadRequest
READY>BUSY_RD [0xbf040000, line 0xbf040000]
646885676000 0 Directory DMA_READ M>M_DRD
[0xbf040000, line 0xbf040000]
646885681500 0 L2Cache MEM_Inv MT>MT_I
[0xbf040000, line 0xbf040000]
646885681500 0 L2Cache MEM_Inv MT_I>MT_I
[0xbf040000, line 0xbf040000]
646885685500 2 L1Cache Inv
M>I [0xbf040000, line 0xbf040000]
646885694000 0 L2Cache WB_Data MT_I>M_I
[0xbf040000, line 0xbf040000]
646885700000 0 Directory Data
M_DRD>M_DRDI [0xbf040000, line 0xbf040000]
panic: Invalid transition
system.ruby.dma_cntrl0 time: 1293771411 addr: 3204710400 event: Data state:
READY
Memory Usage: 1584496 KBytes
Program aborted at tick 646885705500
Any suggestions?
best regards,
Muhammad
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20170612/3bc91ba4/attachment-0001.html>
------------------------------
Message: 2
Date: Mon, 12 Jun 2017 08:10:23 +0000
From: Nikos Nikoleris <[email protected]>
To: gem5 users mailing list <[email protected]>
Subject: Re: [gem5-users] Invalid transition DMA controller in NoC
Message-ID:
<am5pr0802mb252978fbb950936927f45098f7...@am5pr0802mb2529.eurprd08.prod.outlook.com>
Content-Type: text/plain; charset="utf-8"
Hi Muhammad,
If I remember correctly, MESI_Two_Level lacks support for multiple DMA
controllers. The request message does not store the source of the packet and
the response doesn't reach the right DMA controller. If you have a look at
MOESI_CMP_directory, the DMA controller (MOESI_CMP_directory-dma.sm) encodes
the source node in the Requestor and RequestorMachine fields which are then
used to route the response. It shouldn't be too hard to add something similar
for the MESI_Two_Level protocol.
Nikos
________________________________
From: gem5-users <[email protected]> on behalf of SHARJEEL KHILJI
<[email protected]>
Sent: 12 June 2017 07:56:51
To: gem5 users mailing list
Subject: [gem5-users] Invalid transition DMA controller in NoC
Hi,
I am running the following system,
scons build/ARM/gem5.debug PROTOCOL=MESI_Two_Level
./build/ARM/gem5.debug --debug-flags ProtocolTrace configs/example/fs.py
--l1d_size=32kB --l1i_size=32kB --num-l2caches 4 --l2_size=1MB
--cacheline_size=64 --machine-type=VExpress_GEM5_V1 --kernel
/home/khilji/gem5/m5/system/binaries/vmlinux-aarch32 --disk-image
/home/khilji/gem5/m5/system/disks/arm-ubuntu-natty-headless.img --dtb-filename
/home/khilji/gem5/m5/system/dtb/armv7_gem5_v1_4cpu.dtb --num-cpus=4 --ruby
--num-dirs=4 --network=garnet2.0 --topology Mesh_XY --mesh-rows 2 --mem-size
1GB --cpu-clock 1GHz
While running this in debug, and booting the linux I get the following invalid
DMA transition.
When DMA controller receives the read request from the DMA sequencer it moves
to the busy read state
but when input response (Data) is received from (Directory/or PUTX L1) the DMA
has already returned to
ready state before Data event occurs. There are three DMA controllers (equal to
dma ports) in the system as specified in config.ini.
Is this because of the fact that one of the controllers issues the read request
to directory and all of the controllers receive the response?
and then those who have not issued the request receive the response while in
ready state which results in exception.
Following is the protocol trace
646885666000 2 L1Cache Load M>M
[0xbda99a00, line 0xbda99a00]
646885667000 2 Seq Begin >
[0x80359d7c, line 0x80359d40] IFETCH
646885668000 2 Seq Done >
[0x80359d7c, line 0x80359d40] 1 cycles
646885668000 2 L1Cache Ifetch S>S
[0x80359d40, line 0x80359d40]
646885670500 1 DMA ReadRequest READY>BUSY_RD
[0xbf040000, line 0xbf040000]
646885676000 0 Directory DMA_READ M>M_DRD
[0xbf040000, line 0xbf040000]
646885681500 0 L2Cache MEM_Inv MT>MT_I
[0xbf040000, line 0xbf040000]
646885681500 0 L2Cache MEM_Inv MT_I>MT_I
[0xbf040000, line 0xbf040000]
646885685500 2 L1Cache Inv M>I
[0xbf040000, line 0xbf040000]
646885694000 0 L2Cache WB_Data MT_I>M_I
[0xbf040000, line 0xbf040000]
646885700000 0 Directory Data M_DRD>M_DRDI
[0xbf040000, line 0xbf040000]
panic: Invalid transition
system.ruby.dma_cntrl0 time: 1293771411 addr: 3204710400 event: Data state:
READY
Memory Usage: 1584496 KBytes
Program aborted at tick 646885705500
Any suggestions?
best regards,
Muhammad
IMPORTANT NOTICE: The contents of this email and any attachments are
confidential and may also be privileged. If you are not the intended recipient,
please notify the sender immediately and do not disclose the contents to any
other person, use it for any purpose, or store or copy the information in any
medium. Thank you.
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20170612/b7301a30/attachment-0001.html>
------------------------------
Message: 3
Date: Mon, 12 Jun 2017 10:27:47 +0200 (CEST)
From: Kleovoulos Kalaitzidis <[email protected]>
To: gem5 users mailing list <[email protected]>
Subject: Re: [gem5-users] Datatype (data-width) of NEON operations for
ARM in Gem5
Message-ID:
<[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
Hello,
I could suggest a way that I have been using for checking access width of load
instructions but I am not sure it could fit for Neon instructions.
So, normally the produced/built file in the generated folder "exec-ns.cc.inc"
contains all the information in detail for any instruction. But you have to
find the macro-representation of the instruction by the decoder files in the
../src/arch/arm/isa and match the instruction name with the macro presented in
the generated file. And following the decoder you can find out how the
instruction is decoded depending on the bit representation, and you can use the
same pattern of the decoder
to identify an instruction beyond strcompare. So, for a given instruction you
can find its macro in the decoder, grep it in the generated files to see its
actual implementation and
sizes etc.
I hope it helps.
--
Kleovoulos Kalaitzidis
Doctorant - Équipe PACAP
Centre de recherche INRIA Rennes - Bretagne Atlantique
Bâtiment 12E, Bureau E321, Campus de Beaulieu,
35042 Rennes Cedex, France
----- Original Message -----
> From: "Gokul Subramanian Ravi" <[email protected]>
> To: [email protected]
> Sent: Friday, June 9, 2017 9:17:35 PM
> Subject: [gem5-users] Datatype (data-width) of NEON operations for ARM in
> Gem5
> Hello all,
> I'm trying to optimize execution for ARM NEON instructions via Gem5 and for
> that I need to be able to identify the data-width of the executing NEON
> operations.
> From the ARM site, the instructions are as follows:
> VADD{cond}.datatype {Qd}, Qn, Qm ----> where datatype is I8, I16, I32, or
> I64.
> I'm identifying different instructions by performing "
> inst->staticInst->disassemble(..)" and then I do some string comparisons to
> figure out instructions I'm interested in. But for NEON instructions, the
> disassemble() doesn't tell me the "datatype".
> Can someone provide pointers as to how I can identify the datatype? I'm
> guessing I can get something from src/arch/arm/* but not sure what I should
> be looking at. Thank you!
> Best,
> Gokul Subramanian Ravi ,
> Graduate Student,
> ECE Dept.,
> University of Wisconsin-Madison
> _______________________________________________
> gem5-users mailing list
> [email protected]
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
gem5-users Info Page - m5
sim<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users>
m5sim.org
Discussion for users of the gem5 simulator. To see the collection of prior
postings to the list, visit the gem5-users Archives. (The current archive ...
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20170612/71ba3397/attachment-0001.html>
------------------------------
Message: 4
Date: Mon, 12 Jun 2017 12:01:12 +0200
From: Oscar Rosell <[email protected]>
To: gem5 users mailing list <[email protected]>, Muzamil Rafique
<[email protected]>
Subject: Re: [gem5-users] BBV file not generated(or found)
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"; Format="flowed"
Hi,
I don't see any evident problem. Have you tried to generate any BBV
file? For example:
./build/ARM/gem5.opt configs/example/se.py -c
./tests/test-progs/hello/bin/arm/linux/hello --simpoint-profile
--simpoint-interval 10000 --fastmem
should work.
Regards,
Oscar
On 09/06/17 19:07, Muzamil Rafique wrote:
> Hi All,
>
> I am trying to generate BBV file for SimPoint creation using the
> following command:
>
> build/X86/gem5.opt configs/example/spec06_config.py --benchmark bzip2
> --benchmark_stdout=m5out/bzip2.out --benchmark_stderr=m5out/bzip2.err
> -I 100000000 --simpoint-profile --simpoint-interval 10000 --fastmem
>
> But at the end of simulation, I am not getting the BBV
> file(simpoint.bb.gz), neither in gem5 run directory nor in output
> directory.
>
> Can anyone help me out with this issue? Am i doing something wrong?
>
> Muzamil
>
>
> _______________________________________________
> gem5-users mailing list
> [email protected]
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
gem5-users Info Page - m5
sim<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users>
m5sim.org
Discussion for users of the gem5 simulator. To see the collection of prior
postings to the list, visit the gem5-users Archives. (The current archive ...
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20170612/a58acf29/attachment-0001.html>
------------------------------
Message: 5
Date: Mon, 12 Jun 2017 12:44:49 +0000
From: Qureshi Yasir Mahmood <[email protected]>
To: gem5 users mailing list <[email protected]>
Subject: Re: [gem5-users] SystemC and GEM5 SE Mode
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"
Hi Matthias,
I think I have a clue to the problem in the TLM and se.py simulation that when
I configure se.py to have TLM memory using configuration parameter
--tlm-memory, and also have some physical memory like SimpleMemory using
--mem-type=SimpleMemory, it only creates the TLM memory port and does not
instantiate the Simple memory. I manually edited the config.ini file to include
both SimpleMemory and the tlm-memory and the helloworld program worked.
So I think there is a bug in se.py that when tlm-memory is used, it doesn't
create any other memory.
Regards
Yasir
-----Original Message-----
From: gem5-users [mailto:[email protected]] On Behalf Of Matthias Jung
Sent: 09 June 2017 00:21
To: gem5 users mailing list <[email protected]>
Subject: Re: [gem5-users] SystemC and GEM5 SE Mode
Hi Yasir,
I just wanted to say that se.py works without problems in the cxx config.
And I confirmed that there is an issue with the TLM setup and se.py.
Regards
Matthias
> Am 08.06.2017 um 14:43 schrieb Qureshi Yasir Mahmood <[email protected]>:
>
> Hi Matthias,
>
> Thank you for the reply. When you say " Using util/cxx_config with se.py or
> fs.py with util/tlm works fine", do you mean I should compile the
> build/examples/slave_port/gem5.sc using cxx_config ?
>
> Regards
> Yasir
>
>
> -----Original Message-----
> From: gem5-users [mailto:[email protected]] On Behalf Of Matthias
> Jung
> Sent: 07 June 2017 23:50
> To: gem5 users mailing list <[email protected]>
> Subject: Re: [gem5-users] SystemC and GEM5 SE Mode
>
> Hi Yasir,
>
> I just had a short look, indeed there is an issue.
> Using util/cxx_config with se.py or fs.py with util/tlm works fine.
> We will have a deeper look into it.
>
> Regards
> Matthias
>
>
>> Am 07.06.2017 um 18:22 schrieb Qureshi Yasir Mahmood <[email protected]>:
>>
>> Hello All,
>>
>> I am trying to setup a GEM5-SystemC co-simulation with gem5 running in SE
>> mode. I have followed the tutorial in /util/tlm/README file and I can run
>> the example provided. But when I try to run GEM5 in SE with TLM enabled, I
>> get the following error,
>>
>> First to build the config file, I run
>>
>> ../../build/ARM/gem5.opt ../../configs/example/se.py
>> --tlm-memory=transactor --mem-type=SimpleMemory --mem-size=512MB
>> --mem-channels=1 -c ../../../helloworld/hevc
>>
>> And then to run
>>
>> bash-4.2$ build/examples/slave_port/gem5.sc m5out/config.ini
>>
>> SystemC 2.3.1-Accellera --- May 31 2017 13:14:37
>> Copyright (c) 1996-2014 by all Contributors,
>> ALL RIGHTS RESERVED
>> ============================================================
>> EventQueue Dump (cycle 0)
>> ------------------------------------------------------------
>> <No Events>
>> ============================================================
>> 0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
>> 0 s (=) : sc_main Start of Simulation
>> warn: ClockedObject: More than one power state change request encountered
>> within the same simulation tick
>> fatal: Out of memory, please increase size of physical memory.
>> Memory Usage: 597116 Kbytes
>>
>>
>> Can anyone please let me know, if I need to have a separate physical memory
>> for this and hence modify the se.py file or just control it through the
>> configuration options ?
>>
>> Regards
>> Yasir
>> _______________________________________________
>> gem5-users mailing list
>> [email protected]
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
> _______________________________________________
> gem5-users mailing list
> [email protected]
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
> _______________________________________________
> gem5-users mailing list
> [email protected]
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
------------------------------
Message: 6
Date: Mon, 12 Jun 2017 13:06:26 +0000
From: Qureshi Yasir Mahmood <[email protected]>
To: gem5 users mailing list <[email protected]>
Subject: [gem5-users] Memory Mapping SE - Virtual to Physical Address
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"
Hi All,
I have a following system in GEM5 SE mode, with ARM , simple physical memory
and an external tlm-memory.
I know the address range of both of the memories as defined in config.ini file.
Now I want to explicitly access the PHY-MEM and also TLM memory, but I am
unable to do that due to virtual address in the SE mode. Is there a way that I
can access both the memories explicitly in C ?
# +----------------+ +-------+ ^
# | System Port | | CPU | |
# +---------+------+ +---+---+ |
# | | | gem5 World
# | +-------+ |
# | | |
# +---------v------v--------------+ |
# | Membus | |
# +-----+---------------+--------+ |
# | | |
# +----v-------+ | |
# |PHY_MEM| | |
# +------------+ | |
# | v
# | External Port
# | ^
# | |
# +---v---+ | TLM World
# | TLM | |
# +--------+ v
Regards
Yasir
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://m5sim.org/cgi-bin/mailman/private/gem5-users/attachments/20170612/e1df1393/attachment-0001.html>
------------------------------
Subject: Digest Footer
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
------------------------------
End of gem5-users Digest, Vol 131, Issue 10
*******************************************
_______________________________________________
gem5-users mailing list
[email protected]
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
