Hi Jason, I used the following commands for MESI Two level and MOESI CMP Directory
*MESI Two level :* scons build/ARM/gem5.opt RUBY=True PROTOCOL=MESI_Two_level build/ARM/gem5.opt -d m5out/1_1 configs/example/fs.py --kernel=vmlinux.smp.ics.arm.asimbench.2.6.35 --disk-image=ARMv7a-ICS-Android.SMP.Asimbench-v3.img --frame-capture -n 4 --caches --l2cache --l1d_size=64kB --l1d_assoc=4 --l1i_size=64kB --l1i_assoc=4 --l2_assoc=16 --l2_size=1MB --mem-size=256MB --cpu-type=DerivO3CPU --cpu-clock=2.8GHz --machine-type=RealView_PBX --os-type=android-ics --mem-type=LPDDR3_1600_x32 --script ~/asimbench/asimbench_boot_scripts/bbench.rcS *MOESI CMP Dir :* scons build/ARM/gem5.opt RUBY=True PROTOCOL=MOESI_CMP_token build/ARM/gem5.opt -d m5out/1_1 configs/example/fs.py --kernel=vmlinux.smp.ics.arm.asimbench.2.6.35 --disk-image=ARMv7a-ICS-Android.SMP.Asimbench-v3.img --frame-capture -n 4 --caches --l2cache --l1d_size=64kB --l1d_assoc=4 --l1i_size=64kB --l1i_assoc=4 --l2_assoc=16 --l2_size=1MB --mem-size=256MB --cpu-type=DerivO3CPU --cpu-clock=2.8GHz --machine-type=RealView_PBX --os-type=android-ics --mem-type=LPDDR3_1600_x32 --script ~/asimbench/asimbench_boot_scripts/bbench.rcS Please help. Regards, Midhun P On 6 July 2017 at 19:51, Jason Lowe-Power <[email protected]> wrote: > Hello, > > What CPU model are you using? Ruby will only work with timing-based CPU > models (e.g., TimingSimpleCPU and O3CPU). Also, if you're using fs/se.py be > sure to specify --ruby on the command line. > > There are two ways you can be sure the system you're executing is using > Ruby. 1) check the config.ini file and make sure there are Ruby caches > created (e.g., CacheMemory, Sequencer, L1Cache_controller). 2) Check the > stats.txt to be sure that the ruby objects are being accessed. The stats > should not all be 0. > > Jason > > On Wed, Jul 5, 2017 at 8:26 PM Midhun P <[email protected]> wrote: > >> I was doing comparison of different cache coherence protocols in gem5. I >> took MESI 2 level, MOESI CMP directory and MOESI CMP token for that. >> Benchmark i used was Moby for ARM Architecture. But in stats i got same >> results for different cache coherence protocols. Please help. >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- Regards, Midhun P mail to : [email protected] [email protected] Mobile : +91-9946001223 <[email protected]>
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