Hi folks,I had a really weird error in my simulations for a while now and finally think I figured out what caused it. So I'd like to share my thoughts and check if I'm right.
First of all a rough description of my setup: I simulate a system with a number of systems that are connected via a xbar (in full system mode). The error only appeared when using the O3 CPU (I guess because only prefetch accesses touched the memory area that was causing this). In the middle of many simulations I ran into the following error message:
gem5.opt: build/X86/mem/packet_access.hh:58: T Packet::getRaw() const [with T = long unsigned int]: Assertion `flags.isSet(STATIC_DATA|DYNAMIC_DATA)' failed.
Which means AFAIK that the packet's data has not been initialized correctly.So I tracked down when this packet was created and ended up at the following point: src/cpu/o3/lsq_unit.hh:611 At this point the LSQ handles split loads that operate on the area of mmapped IPRs. It appears to me that the code path of a split load has not been tested so far, since the data_pkt's actual data member (and likewise the static_data or dynamic_data flags) is not set if we take the else branch in line 616. But still a WritebackEvent is scheduled afterwards, which will cause the error seen above once it is processed.
To fix this I simply moved the data member assignment out of the if clause: --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh@@ -610,8 +610,8 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
Cycles delay(0);
PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq);
+ data_pkt->dataStatic(load_inst->memData);
if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
- data_pkt->dataStatic(load_inst->memData);
delay = TheISA::handleIprRead(thread, data_pkt);
} else {
This way the WritebackEvent will touch a packet with a valid data
buffer. Does that make sense for anyone who knows a bit more of the
implementation of gem5's CPU models?
Thanks, Matthias
smime.p7s
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