dear all, I'm trying to modify the hit latency ,miss delay of TLB . I have read the source code about TLB for SimpleTimingCPU Two place confused me .First I can't find the latency about TLB hit lentency, is just one cycle for hit latency if it hit in the TLB ? or the gem5 ignore the hit latency. How can I add the hit latency into the total simulation time .Second, I can't seem to find is what the latency of a DTLB miss is . I simulate spec200 mcf and pagerank in x86/fs in different TLB size, and I find the total simulate time is different ,I guess this is because of the TLB missing penalty caused ,if it is, how can I get the miss delay ? I know in x86 fs ，there's a TLB walker component which does memory accesses to look up the entry in the page tables .is TLB miss delay determined by those accesses? Thanks in advance regards lily
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