Hi Oscar.
Thanks your rapid reply
First of all ,you are right ,the fs mode commend line edit error, because of my
careless
Second , as you except ,the number of instructions executed is different.
Then, I change my rcS file followed you said ， I get a new stats,txt ,the
sim_seconds is the actual simulation time for this program ,Am I right?
this is my rcs file
#!/bin/sh
m5 resetstats
/arraywritenew
m5 exit
common line：build/X86/gem5.opt configs/example/fs.py --cpu-type=TimingSimpleCPU
--caches --script=configs/boot/arraywrite.rcS
this is a part of my stats.txt
sim_seconds 0.004447 #
Number of seconds simulated
sim_ticks 4447491000 #
Number of ticks simulated
final_tick 5311293823000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
system.cpu.dtb.rdAccesses 305360 #
TLB accesses on read requests
system.cpu.dtb.wrAccesses 227953 #
TLB accesses on write requests
system.cpu.dtb.rdMisses 556 #
TLB misses on read requests
system.cpu.dtb.wrMisses 175 #
TLB misses on write requests
--------- End Simulation Statistics ----------
Next I changed rcS file again,it has two Simulation Statistics ,Is sim_seconds
( 0.004455 ) the actual simulation time for this program? why different
the sim_seconds ( 0.004447 )
this is my rcs file
m5 resetstats
/arraywritenew
m5 dumpstats
m5 exit
common line：build/X86/gem5.opt configs/example/fs.py --cpu-type=TimingSimpleCPU
--caches --script=configs/boot/arraywrite.rcS
this is a part of my stats.txt
---------- Begin Simulation Statistics ----------
sim_seconds 0.004455 #
Number of seconds simulated
sim_ticks 4454880000 #
Number of ticks simulated
final_tick 5311301280000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
system.cpu.dtb.rdAccesses 306413 #
TLB accesses on read requests
system.cpu.dtb.wrAccesses 228544 #
TLB accesses on write requests
system.cpu.dtb.rdMisses 556 #
TLB misses on read requests
system.cpu.dtb.wrMisses 175 #
TLB misses on write requests
--------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.006399 #
Number of seconds simulated
sim_ticks 6399292000 #
Number of ticks simulated
final_tick 5313245692000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated tickssystem.cpu.dtb.rdAccesses
430950 # TLB accesses on read requests
system.cpu.dtb.wrAccesses 323985 #
TLB accesses on write requests
system.cpu.dtb.rdMisses 825 #
TLB misses on read requests
system.cpu.dtb.wrMisses 249 #
TLB misses on write requests
--------- End Simulation Statistics ----------
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