Hi all, I am trying to simulate a system with a shared L1 cache. I created two noncoherent crossbars, one for L1D and one for L1I and connected them to each CPU's dcache_port and icache_port, respectively. When using an O3CPU to simulate a full system I get the following error:
gem5.opt: build/X86/mem/xbar.cc:190: bool BaseXBar::Layer<SrcType, DstType>::tryTiming(SrcType*) [with SrcType = SlavePort; DstType = MasterPort]: Assertion `std::find(waitingForLayer.begin(), waitingForLayer.end(), src_port) == waitingForLayer.end()' failed. I read in an archived mail that the ports in an O3CPU have to be connected to a cache and not a crossbar. If so, is there any way that I can still realize a shared L1 cache? Thanks, Haiyang
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