Dear All,
I would like to configure the McPat xml file for obtaining the benchmark
power analysis from the gem5 FS stats. However, the current stat file has
lots of missing parameter in corresponding to Mcpat xml file. It will be
very kind to me if anyone can provide me the script to generate the xml
file from the current stats files or I would like to know how I can find
the value/results of the attached parameters or stats from the gem5 stats
or ini or json file.
Thanks a lot.
Best regards,
F. A. Faisal
<component id="system.mem" name="mem">
<!-- Main memory property -->
<param name="device_clock" value="200"/>
<param name="peak_transfer_rate" value="6400"/>
<param name="capacity_per_channel" value="4096"/>
<param name="Block_width_of_DRAM_chip" value="64"/>
<param
name="output_width_of_DRAM_chip" value="8"/>
<param name="page_size_of_DRAM_chip" value="8"/>
<param name="burstlength_of_DRAM_chip" value="8"/>
<stat name="memory_accesses" value="0"/>
<stat name="memory_reads" value="0"/>
<stat name="memory_writes" value="0"/>
</component>
<component id="system.mc" name="mc">
<param name="peak_transfer_rate" value="1600"/>
<param name="block_size" value="16"/><!--B-->
<param name="addressbus_width" value="32"/>
<stat name="memory_accesses" value="6666"/>
<stat name="memory_reads" value="3333"/>
<stat name="memory_writes" value="3333"/>
</component>
<component id="system.L20" name="L20">
<stat name="read_accesses" value="stats.system.l2.ReadReq_accesses"/>
<stat name="write_accesses" value="stats.system.l2.ReadExReq_accesses"/>
<stat name="read_misses" value="stats.system.l2.ReadReq_misses"/>
<stat name="write_misses" value="stats.system.l2.ReadExReq_misses"/>
<stat name="conflicts" value="stats.system.l2.replacements"/>
<stat name="duty_cycle" value="0.5"/>
</component>
<component id="system.core0.dcache" name="dcache">
<param name="dcache_config"
value="config.system.cpu.dcache.size,config.system.cpu.dcache.tags.block_size,config.system.cpu.dcache.assoc,1,1,config.system.cpu.dcache.response_latency,config.system.cpu.dcache.tags.block_size,0"/>
<param name="buffer_sizes"
value="config.system.cpu.dcache.mshrs,config.system.cpu.dcache.mshrs,config.system.cpu.dcache.mshrs,config.system.cpu.dcache.mshrs"/>
miss_buffer_size(MSHR),fill_buffer_size,prefetch_buffer_size,wb_buffer_size-->
<stat name="read_accesses"
value="stats.system.cpu.dcache.ReadReq_accesses::total"/>
<stat name="write_accesses"
value="stats.system.cpu.dcache.WriteReq_accesses::total"/>
<stat name="read_misses"
value="stats.system.cpu.dcache.ReadReq_misses::total"/>
<stat name="write_misses"
value="stats.system.cpu.dcache.WriteReq_misses::total"/>
<stat name="conflicts"
value="stats.system.cpu.dcache.tags.replacements"/>
</component>
<component id="system.core0.dtlb" name="dtlb">
<param name="number_entries" value="config.system.cpu.dtb.size"/>
</component>
<component id="system.core0.icache" name="icache">
<param name="icache_config"
value="config.system.cpu.icache.size,config.system.cpu.icache.tags.block_size,config.system.cpu.icache.assoc,1,1,config.system.cpu.icache.response_latency,config.system.cpu.icache.tags.block_size,0"/>
<param name="buffer_sizes"
value="config.system.cpu.icache.mshrs,config.system.cpu.icache.mshrs,config.system.cpu.icache.mshrs,config.system.cpu.icache.mshrs"/>
</component>
<stat name="ROB_reads" value="stats.system.cpu.rob.rob_reads"/>
<stat name="ROB_writes" value="stats.system.cpu.rob.rob_writes”/>
<stat name="rename_reads"
value="stats.system.cpu.rename.int_rename_lookups"/> <!--lookup in renaming
logic -->
<stat name="rename_writes"
value="int(stats.system.cpu.rename.RenamedOperands *
stats.system.cpu.rename.int_rename_lookups /
stats.system.cpu.rename.RenameLookups)"/><!--update dest regs. renaming logic
-->
<stat name="fp_rename_reads"
value="stats.system.cpu.rename.fp_rename_lookups"/>
<stat name="fp_rename_writes"
value="int(stats.system.cpu.rename.RenamedOperands *
stats.system.cpu.rename.fp_rename_lookups /
stats.system.cpu.rename.RenameLookups)"/>
<!-- decode and rename stage use this, should be total ic - nop -->
<!-- Inst window stats -->
<stat name="inst_window_reads"
value="stats.system.cpu.iq.int_inst_queue_reads"/>
<stat name="inst_window_writes"
value="stats.system.cpu.iq.int_inst_queue_writes"/>
<stat name="inst_window_wakeup_accesses"
value="stats.system.cpu.iq.int_inst_queue_wakeup_accesses"/>
<stat name="fp_inst_window_reads"
value="stats.system.cpu.iq.fp_inst_queue_reads"/>
<stat name="fp_inst_window_writes"
value="stats.system.cpu.iq.fp_inst_queue_writes"/>
<stat name="fp_inst_window_wakeup_accesses"
value="stats.system.cpu.iq.fp_inst_queue_wakeup_accesses"/>
<!-- RF accesses -->
<stat name="int_regfile_reads"
value="stats.system.cpu.int_regfile_reads"/>
<stat name="float_regfile_reads"
value="stats.system.cpu.fp_regfile_reads"/>
<stat name="int_regfile_writes"
value="stats.system.cpu.int_regfile_writes"/>
<stat name="float_regfile_writes"
value="stats.system.cpu.fp_regfile_writes"/>
<param name="phy_Regs_IRF_size" value="config.system.cpu.numPhysIntRegs"/>
<param name="phy_Regs_FRF_size"
value="config.system.cpu.numPhysFloatRegs"/>
<param name="store_buffer_size" value="config.system.cpu.SQEntries"/>
<param name="load_buffer_size" value="config.system.cpu.LQEntries"/>
<param name="memory_ports" value="2"/>
<param name="RAS_size" value="config.system.cpu.branchPred.RASSize"/>
<stat name="committed_int_instructions"
value="stats.system.cpu.commit.int_insts"/>
<stat name="committed_fp_instructions"
value="stats.system.cpu.commit.fp_insts"/>
<stat name="total_instructions" value="stats.system.cpu.iq.iqInstsIssued"/>
<stat name="int_instructions"
value="stats.system.cpu.iq.FU_type_0::No_OpClass +
stats.system.cpu.iq.FU_type_0::IntAlu + stats.system.cpu.iq.FU_type_0::IntMult
+ stats.system.cpu.iq.FU_type_0::IntDiv +
stats.system.cpu.iq.FU_type_0::IprAccess"/>
<stat name="fp_instructions"
value="stats.system.cpu.iq.FU_type_0::FloatAdd +
stats.system.cpu.iq.FU_type_0::FloatCmp +
stats.system.cpu.iq.FU_type_0::FloatCvt +
stats.system.cpu.iq.FU_type_0::FloatMult +
stats.system.cpu.iq.FU_type_0::FloatDiv +
stats.system.cpu.iq.FU_type_0::FloatSqrt"/>
<param name="number_of_BTB" value="2"/>
<component id="system.core0.BTB" name="BTB">
<param name="BTB_config" value="5120,4,2,1, 1,3"/>
<stat name="read_accesses"
value="stats.system.cpu.branchPred.BTBLookups"/>
<stat name="write_accesses" value="stats.system.cpu.commit.branches"/>
</component>
<component id="system.L1Directory0" name="L1Directory0">
<param name="Directory_type" value="0"/>
<param name="Dir_config"
value="4096,2,0,1,100,100, 8"/>
<param name="buffer_sizes" value="8, 8, 8, 8"/>
<param name="clockrate" value="3400"/>
<param name="ports" value="1,1,1"/>
<param name="device_type" value="0"/>
<stat name="read_accesses" value="800000"/>
<stat name="write_accesses" value="27276"/>
<stat name="read_misses" value="1632"/>
<stat name="write_misses" value="183"/>
<stat name="conflicts" value="20"/>
</component>
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