Hello, I am working with DRAM configuration on gem5. My aim is to look closely the bank configurations in gem5's DRAM architecture. Where would I find the architectural configurations of DRAM banks like bank arrangement topology as my aim is to modify bank status during simulation. I would really appreciate it if you point me to the relevant code or documentation.
Thank you, Kaustav Goswami, Indian Institute of Information Technology Guwahati.
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
