I don't know of one, sorry. If all you want is to dump and reset stats, though, and you don't need the binary to have the values of those stats, then I have done something like this in the past. If you look in sim/pseudo_inst.hh, there's a function named dumpstats that you can call whenever a write to a particular CSR is performed. There should be functions there to reset stats as well.
If you just want it to be done periodically, you can modify se.py to call m5.dumpresetstats() (or something like that) before starting the simulation, and then you don't have to modify any C++ code or your binary. On Tue, Dec 19, 2017 at 9:54 PM, Vanchinathan Venkataramani < dcsv...@gmail.com> wrote: > Dear Alec > > Thanks a lot for your prompt reply. I looked at the CSR counters and it > looks to me that I cannot find number of integer, load, store instructions > executed separately. > > Ideally, if I can reset and dump stats using m5_dumpstats and > m5_resetstats, I can get detailed information on instruction executed per > type in one go. But now this is not available. Is there *any tutorial* that > can be used for *implementing* this? > > Thanks a lot once again. > > V Vanchinathan > > On Wed, Dec 20, 2017 at 2:44 AM, Alec Roelke <ar...@virginia.edu> wrote: > >> Hi Vanchinathan, >> >> At the moment, there is not a patch for m5op support for RISC-V. If you >> want binaries to have access to performance counts, the best way to do that >> would probably be to add CSRs for them and have those CSRs return the >> values of the corresponding stats when read, like INSTRET, CYCLE, and TIME >> do. >> >> -Alec Roelke >> >> On Tue, Dec 19, 2017 at 1:25 AM, Vanchinathan Venkataramani < >> dcsv...@gmail.com> wrote: >> >>> Dear all >>> >>> I would like to collect performance counters for a RISCV binary in gem5. >>> >>> Is there a util/m5 patch for generating m5ops for RISCV? Any help really >>> appreciated. >>> >>> Best regards >>> V Vanchinathan >>> >> >> > > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >
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