Dear Nikos,
Many thanks for your reply. I have not intentionally
specified any pre-fetcher.
But the invalid program counter problem is solved by your hint. In cache.cc
file, inside recvTimingReq() function, i saw one new request is generated,
for software prefetch packet. By copying the program counter value (as
highlighted in code below), i was able to get valid program counter values.
Does this mean there is some by default Software
prefetcher?
Many Thanks
Best Regards
Avais
if (pkt->cmd.isSWPrefetch()) {
assert(needsResponse);
assert(pkt->req->hasPaddr());
assert(!pkt->req->isUncacheable());
// There's no reason to add a prefetch as an additional target
// to an existing MSHR. If an outstanding request is already
// in progress, there is nothing for the prefetch to do.
// If this is the case, we don't even create a request at all.
PacketPtr pf = nullptr;
if (!mshr) {
// copy the request and create a new SoftPFReq packet
RequestPtr req = new Request(pkt->req->getPaddr(),
pkt->req->getSize(),
pkt->req->getFlags(),
pkt->req->masterId());
if(!pkt->req->hasPC())
invalid_onmiss[Request::wbMasterId]++;
else
req->setPC(pkt->req->getPC());
pf = new Packet(req, pkt->cmd);
pf->allocate();
assert(pf->getAddr() == pkt->getAddr());
assert(pf->getSize() == pkt->getSize());
}
On Mon, Jan 15, 2018 at 8:23 PM, Nikos Nikoleris <[email protected]>
wrote:
> Hi Avais,
>
> Are you using any kind of prefetcher? Requests issued by a prefetcher
> won't have a valid PC either.
>
> Generally the PC is stored in the request object of a packet. If the
> request has been instantiated and initialized in the memory system
> (e.g., writebacks, prefetches), it won't have a valid PC.
>
> Thanks,
>
> Nikos
>
> On 01/15/18 11:17, Muhammad Avais wrote:
>
>> Dear Nikos,
>>
>> Many thanks for your reply. Actually, I wanted to see
>> the Program counter value of Load/Store instructions that brought blocks
>> in L2 cache
>> For evicted blocks from L1 cache, i have copied the Program counter
>> value in Request of Packet in writebackblock() function. Now, I can see
>> the Program counter of L2 blocks brought into L2 because of writeback miss
>>
>> Problem is for blocks brought into L2 because of miss in L2. For some
>> benchmarks(astar, gobmk), i see invalid PC value for many packets.
>>
>> How can i modify gem5 to get valid PC value for blocks brought into L2
>> because of miss in L2
>>
>> Many Thanks,
>> Best Regards,
>> Avais
>>
>> On Sat, Jan 13, 2018 at 12:21 AM, Nikos Nikoleris
>> <[email protected] <mailto:[email protected]>> wrote:
>>
>> Hi Avais,
>>
>> If I remember correctly, this is expected. Evictions, for example,
>> won't
>> have a valid program counter.
>>
>> Nikos
>>
>> On 01/12/18 11:44, hassan yamin wrote:
>>
>> For the packets you are getting invalid program counter, can you
>> check
>> is it read or write packet?
>>
>> On Jan 12, 2018 8:20 PM, "Muhammad Avais"
>> <[email protected] <mailto:[email protected]>
>> <mailto:[email protected] <mailto:[email protected]>>>
>> wrote:
>>
>> Dear All,
>> I want to get the Program counter value of
>> packets at
>> some points in gem5.
>> For some packets, i am getting invalid program counter
>> value(in
>> cache::handlefill() function mostly)
>>
>> Can anyone suggest, how can i get valid program counter.
>>
>>
>> Many Thanks
>> Best Regards
>> Avais
>>
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