Hi Varun, Some comments inline below.
On Tue, Feb 6, 2018 at 11:33 PM Saivarun R <rsvaru...@gmail.com> wrote: > Hi Jason, > > As you pointed out, I went through the dram_ctrl.cc file and spent some > time designing the implementation. I want to know if what I understood is > correct regarding the implementation or not. > > Firstly, there is need of a block structure in dram_ctrl to hold the data. > Then a tag store array for tags. > You will need tags in your cache, but the DRAM controller does not need tags. > Most importantly, implementing the Master port functionalities. Though I > looked at your tutorials about the ports, I'm unable to visualize the > interactions possible in the current scenario. I need help in this regard. > See http://learning.gem5.org/book/part2/memoryobject.html#gem5-master-and-slave-ports. Beyond those pictures and the example code, I'm not sure I can give you more guidance. > > And thinking further, I have an idea of creating a wrapper class for the > cacheblks in gem5, which will arrange the cacheblks (of cacheline size 64 > bytes) to form a larger "cache-line" (arrange 16 cacheblks to form a 1KB > cache-line size) in the cache. Is it possible to realize different > cacheline sizes with this idea. > Sure. Search for sub-blocked caches. This is what you would be implementing. > > Regards > Varun > _______________________________________________ > gem5-users mailing list > firstname.lastname@example.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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