See https://gem5.googlesource.com/public/gem5/+/master/configs/common/MemConfig.py#135 for an example of using interleaved ranges.
One thing to keep in mind is that if you use the same bits for interleaving as indexing the cache you will be artificially constraining the size of your cache. (E.g., if you use bit 6 for interleaving and bits 6-10 for indexing then you will never use any even sets in the first bank or any odd sets in the second bank.) This can also affect your actual associativity. Jason ----------- Jason Lowe-Power Assistant Professor, Computer Science Department University of California, Davis 3049 Kemper Hall https://faculty.engineering.ucdavis.edu/lowepower/ On Fri, Feb 2, 2018 at 3:26 PM Haiyang Han < haiyang....@eecs.northwestern.edu> wrote: > Hi all, > > In the BaseCache the address range is defined as > "VectorParam.AddrRange([AllMemory])". How should I set that if I want 4 > separate cache banks with interleaved address? Should I do something like: > addr_ranges = start:finish:high bit used for interleaving:0:number of > interleaving bits:matching value? > > Thanks > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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