Hello all,
I was trying to run the simulation with following condition:

  *   First fast forward to N instructions (38 million in this case) and then 
use detailed CPU to run another 10M instruction.
  *   My understanding is, when CPU is fast forwarded to N instructions, all 
the registers, buffers and caches would be filled with correct state/value for 
the processor before switching to Detailed CPU.
I am using the following command:
mxm@ce6304:gem5$ ./script
Running 401.bzip2 benchmark
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (2048 Mbytes)
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Feb 19 2018 11:16:26
gem5 started Feb 22 2018 15:28:26
gem5 executing on ce.edu, pid 95882
command line: ./build/RISCV/gem5.opt -d ./Testing/401.bzip2_out/fast_forward 
./configs/example/se.py -I 10000000 --fast-forward=38000000 
--cpu-type=DerivO3CPU --caches --l1d_size=8kB --l1i_size=2kB --l1d_assoc=1 
--l1i_assoc=1 -c test/Speckle/build/401.bzip2_test/bzip2_base.riscv -o 
'input.program 5'

Global frequency set at 1000000000000 ticks per second
warn: Unknown operating system; assuming Linux.
0: system.remote_gdb: listening for remote gdb on port 7000
info: Entering event queue @ 0.  Starting simulation...
Switch at instruction count:38000000
Loading Input Data

Problem is, the simulator is stuck here for the past few hours and there is no 
update on the console. I am confused whether I am running the simulation 
Also, what if I used a TimingSimpleCPU for the fast-forwarding instead of 
default AtomicCPU? What difference will it make in the processor before 
switching to Detailed CPU?

Kindly help.

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