[gem5-users] How to set cache access latencies in Ruby mode？

[li lan]

 Hi all，

I'm doing simulations with the Ruby memory system and

MESI_Two_Level(MESI_CMP_directory) protocol. I want to set L1 Cache
access latency (for example 3 cycles)and L2 Cache access latency(15
cycles), but i do not understand how to do that. Because there are
three files containing latencies.


1. src/mem/ruby/system/Sequencer.py:


    # TODO: Latencies should be migrated into each top-level cache controller

    70 
<http://repo.gem5.org/gem5/file/5102ba06fca5/src/mem/ruby/system/Sequencer.py#l70>
   icache_hit_latency = Param.Cycles(1, "Inst cache hit latency")

    71 
<http://repo.gem5.org/gem5/file/5102ba06fca5/src/mem/ruby/system/Sequencer.py#l71>
   dcache_hit_latency = Param.Cycles(1, "Data cache hit latency")

2. src/mem/protocol/MESI_Two_Level-L1Cache.sm:


machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")


    35 
<http://repo.gem5.org/gem5/file/5102ba06fca5/src/mem/protocol/MESI_Two_Level-L1cache.sm#l35>
   Cycles l1_request_latency := 2;

    36 
<http://repo.gem5.org/gem5/file/5102ba06fca5/src/mem/protocol/MESI_Two_Level-L1cache.sm#l36>
   Cycles l1_response_latency := 2;

    37 
<http://repo.gem5.org/gem5/file/5102ba06fca5/src/mem/protocol/MESI_Two_Level-L1cache.sm#l37>
   Cycles to_l2_latency := 1;

3. src/mem/protocol/MESI_Two_Level-L2Cache.sm:

 machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP")

    30 
<http://repo.gem5.org/gem5/file/5102ba06fca5/src/mem/protocol/MESI_Two_Level-L2cache.sm#l30>
 : CacheMemory * L2cache;

    31 
<http://repo.gem5.org/gem5/file/5102ba06fca5/src/mem/protocol/MESI_Two_Level-L2cache.sm#l31>
   Cycles l2_request_latency := 2;

    32 
<http://repo.gem5.org/gem5/file/5102ba06fca5/src/mem/protocol/MESI_Two_Level-L2cache.sm#l32>
   Cycles l2_response_latency := 2;

    33 
<http://repo.gem5.org/gem5/file/5102ba06fca5/src/mem/protocol/MESI_Two_Level-L2cache.sm#l33>
   Cycles to_l1_latency := 1;

I wonder which latency stands for L1 Cache access latency and which one
stands for L2 Cache access latency?


Thank you very much for your help!

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