Hi All, I am trying to make changes in MSI Cache Coherence protocol. My objective is to study the statistics and find if there is a fault in the system (especially the invalidation signals caused due to this).
What I want to do is for a particular processor, whenever there is a load instruction, I want to convert it to store instruction with the same data, so that if there is a miss, then an invalidation is send to all the sharers of that block present in the directory. I understood that all the requests from Processor arrives at mandatory queue. But I am unable to figure out how to implant this error at a processor level, so that I can achieve my objective. Thanks, Arka Roy, Undergraduate Student, NIT Durgapur, India
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