Hi, Jason

Sorry for my unclear description before. For our workload,
the switch_cpus.dtb's miss rate for 64 tlb entries is 154654 / 1589214 =
9.74%; the miss rate for 1048576 tlb entries is 154360 / 1583757 = 9.73%.
Both are running for 20ms warm up in atomic mode and 2.5ms real simulation
with O3CPU. They are practically identical and very high especially for
1048576 entries with only 1MB heap size.

Any idea or suggestions? Please let me know if other statistics or config
information will be helpful.

best,
Da

On Mon, May 28, 2018 at 12:03 PM, Jason Lowe-Power <ja...@lowepower.com>
wrote:

> Hi Da,
>
> "For size > 512, the whole stats.txt is identical."
>
> This isn't surprising. 512*4KB = 2MB. So, if your workload is only 1MB
> when you have at least 512 entries you are only seeing compulsory (cold)
> misses. Try running larger workloads and/or workloads with more reuse.
>
> Cheers,
> Jason
>
> On Thu, May 24, 2018 at 9:11 AM Da Zhang <d...@vt.edu> wrote:
>
>> I am using FS mode.
>>
>> On Thu, May 24, 2018 at 12:00 PM, Jason Lowe-Power <ja...@lowepower.com>
>> wrote:
>>
>>> Hi Da,
>>>
>>> Are you using SE mode or FS mode? IIRC, the TLB size does nothing in SE
>>> mode (it doesn't use a TLB). The TLB is only used in FS mode.
>>>
>>> Jason
>>>
>>> On Thu, May 24, 2018 at 8:45 AM Da Zhang <d...@vt.edu> wrote:
>>>
>>>> Hey guys,
>>>>
>>>> I tried to increase the dtb size (i.e., number of tlb entries) for our
>>>> research. However, the stats.txt for the different dtb size
>>>> (64,128,256,512,1024,2048,1048576) is practical identical or
>>>> identical. For size < 512, the system.switch_cpus.dtb.rdAccesses difference
>>>> is only several hundred. For size > 512, the whole stats.txt is identical.
>>>> I am working for the X86 architecture. I change the size in X86TLB.py to
>>>> increase the dtb size. By checking the config.ini file, I see the size is
>>>> set as expected (under system.cpu.dtb). Any clue?
>>>>
>>>> Thanks in advance.
>>>>
>>>> Best,
>>>> Da
>>>>
>>>>
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