Hello everyone,

I have been reading several posts in this forum and the gem5 documentation,
I am new with gem5, I  have to work with memory subsystem and I have
already changed characteristics on main memory and cache memory as train.
However I have some questions that I have not answered reading the forum:

1. gem5 has two memory models, i.e. classic and ruby. I need to change the
read and write latencies, to be asymmetric for modeling an NVM memory. I
know it is super easy in the classic model, but I also need to change the
coherence protocol to avoid writes in some cache level, i.e the LLC is
supposed to be an NVM so I do not want to always write on it.

Is it possible to have asymmetric latencies with Ruby model? I tried it,
but I got an error when I simulate in full-system mode, I added asymmetric
latencies and stall the execution if the bank is busy, but many stalls
caused an error. In classic model I do not have problems but the cache
manage is fixed, I think it is a mess to change the cache manage to avoid
writes in one level.

2. I need to access cache line, I need to count the modified bits. Is it
possible to access cache line in both memory models?

3. I have read papers where people use NVMain with gem5, is possible to use
it as cache memory only for LLC? L1 and L2 will be SRAM.

4. I have read some posts where people talk about an unified memory model
for gem5, are there people working on it?

Thanks in advance for any help.

--
All the best
                   Rich
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