Hi Ciro,
I'm using a modified version of the fs.py to do some simulations for energy
control.
I couldn't find the system.iobus.forward_latency error.
============fs_dvfs_4core.py===
# Copyright (c) 2010-2013 ARM Limited
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# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
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# this software without specific prior written permission.
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Ali Saidi
# Brad Beckmann
import optparse
import sys
import m5
from m5.defines import buildEnv
from m5.objects import *
from m5.util import addToPath, fatal
addToPath('../')
from ruby import Ruby
from common.FSConfig import *
from common.SysPaths import *
from common.Benchmarks import *
from common import Simulation
from common import CacheConfig
from common import MemConfig
from common import CpuConfig
from common.Caches import *
from common import Options
# Check if KVM support has been enabled, we might need to do VM
# configuration if that's the case.
have_kvm_support = 'BaseKvmCPU' in globals()
def is_kvm_cpu(cpu_class):
return have_kvm_support and cpu_class != None and \
issubclass(cpu_class, BaseKvmCPU)
def build_test_system(np):
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus,
bm[0],
options.ruby)
elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
options.dtb_filename,
bare_metal=options.bare_metal)
if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True
else:
fatal("Incapable of building %s full system!",
buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = test_sys.voltage_domain)
# Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain(voltage =
['1.1V','1.085V','1.07V','1.055V','1.04V','1.025V','1.01V','0.995V','0.98V','0.965V','0.95V','0.94V','0.925V','0.915V','0.9V','0.89V','0.875V','0.865V','0.855V','0.845V','0.835V','0.825V','0.815V','0.805V','0.8V','0.8V','0.8V'])
# Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(clock =
['2.2656GHz','2.1888GHz','2.112GHz','2.0352GHz','1.9584GHz','1.8816GHz','1.8048GHz','1.728GHz','1.6512GHz','1.5744GHz','1.4976GHz','1.4208GHz','1.344GHz','1.2672GHz','1.1904GHz','1.1136GHz','1.0368GHz','960MHz','883.2MHz','806.4MHz','729.6MHz','652.8MHz','576MHz','499.2MHz','422.4MHz','345.6MHz','300MHz'],
voltage_domain =
test_sys.cpu_voltage_domain,
domain_id = 0)
test_sys.dvfs_handler.domains = test_sys.cpu_clk_domain
test_sys.dvfs_handler.enable = 1
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
if options.script is not None:
test_sys.readfile = options.script
if options.lpae:
test_sys.have_lpae = True
if options.virtualisation:
test_sys.have_virtualization = True
test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain,
cpu_id=i)
for i in xrange(np)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
if options.ruby:
# Check for timing mode because ruby does not support atomic
accesses
if not (options.cpu_type == "detailed" or options.cpu_type ==
"timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
Ruby.create_system(options, test_sys, test_sys.iobus,
test_sys._dma_ports)
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(clock =
options.ruby_clock,
voltage_domain =
test_sys.voltage_domain)
for (i, cpu) in enumerate(test_sys.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
cpu.clk_domain = test_sys.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
cpu.interrupts.int_master =
test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.int_slave =
test_sys.ruby._cpu_ports[i].master
test_sys.ruby._cpu_ports[i].access_phys_mem = True
# Create the appropriate memory controllers
# and connect them to the IO bus
test_sys.mem_ctrls = [TestMemClass(range = r) for r in
test_sys.mem_ranges]
for i in xrange(len(test_sys.mem_ctrls)):
test_sys.mem_ctrls[i].port = test_sys.iobus.master
else:
if options.caches or options.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
else:
test_sys.iobridge = Bridge(delay='50ns', ranges =
test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
# Sanity check
if options.fastmem:
if TestCPUClass != AtomicSimpleCPU:
fatal("Fastmem can only be used with atomic CPU!")
if (options.caches or options.l2cache):
fatal("You cannot use fastmem in combination with caches!")
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].fastmem = True
if options.checker:
test_sys.cpu[i].addCheckerCpu()
test_sys.cpu[i].createThreads()
CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys)
return test_sys
def build_drive_system(np):
# driver system CPU is always simple, so is the memory
# Note this is an assignment of a class, not an instance.
DriveCPUClass = AtomicSimpleCPU
drive_mem_mode = 'atomic'
DriveMemClass = SimpleMemory
if buildEnv['TARGET_ISA'] == 'alpha':
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'mips':
drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'sparc':
drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'x86':
drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1])
elif buildEnv['TARGET_ISA'] == 'arm':
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
bm[1] , #)
options.dtb_filename,
bare_metal=options.bare_metal)
# Create a top-level voltage domain
drive_sys.voltage_domain = VoltageDomain(voltage = '2V')
# Create a source clock for the system and set the clock period
drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = drive_sys.voltage_domain)
# Create a CPU voltage domain
drive_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period
drive_sys.cpu_clk_domain = SrcClockDomain(clock = '4GHz',
#options.cpu_clock,
voltage_domain =
drive_sys.cpu_voltage_domain)
#
drive_sys.cpu_voltage_domain,
# domain_id = 0)
# drive_sys.dvfs_handler.domains = drive_sys.cpu_clk_domain
# drive_sys.dvfs_handler.enable = 0
drive_sys.readfile =
"/home/ju/gem5/recent/gem5-stable/scripts/ael-server-fifo_loss_0.rcS"
# drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
# cpu_id=0)
drive_sys.cpu = [DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
cpu_id=i)
for i in xrange(np)]
# For now, assign all the CPUs to the same clock domain
# test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain,
cpu_id=i)
# for i in xrange(np)]
for i in xrange(np):
if options.fastmem:
drive_sys.cpu[i].fastmem = True
if options.checker:
drive_sys.cpu[i].addCheckerCpu()
drive_sys.cpu[i].createThreads()
drive_sys.cpu[i].createInterruptController()
# drive_sys.cpu[i].connectAllPorts(drive_sys.membus)
# drive_sys.cpu.createThreads()
# drive_sys.cpu.createInterruptController()
# drive_sys.cpu.connectAllPorts(drive_sys.membus)
# if options.fastmem:
# drive_sys.cpu.fastmem = True
if options.kernel is not None:
#drive_sys.kernel = binary(options.kernel)
drive_sys.kernel = binary('vmlinux')
if is_kvm_cpu(DriveCPUClass):
drive_sys.vm = KvmVM()
# drive_sys.iobridge = Bridge(delay='50ns',
# ranges = drive_sys.mem_ranges)
# drive_sys.iobridge.slave = drive_sys.iobus.master
# drive_sys.iobridge.master = drive_sys.membus.slave
drive_sys.iocache = IOCache(addr_ranges = drive_sys.mem_ranges)
drive_sys.iocache.cpu_side = drive_sys.iobus.master
drive_sys.iocache.mem_side = drive_sys.membus.slave
# Create the appropriate memory controllers and connect them to the
# memory bus
drive_sys.mem_ctrls = [DriveMemClass(range = r)
for r in drive_sys.mem_ranges]
for i in xrange(len(drive_sys.mem_ctrls)):
drive_sys.mem_ctrls[i].port = drive_sys.membus.master
drive_sys.init_param = options.init_param
CacheConfig.config_cache(options, drive_sys)
# MemConfig.config_mem(options, drive_sys)
return drive_sys
# Add options
parser = optparse.OptionParser()
Options.addCommonOptions(parser)
Options.addFSOptions(parser)
# Add the ruby specific and protocol specific options
if '--ruby' in sys.argv:
Ruby.define_options(parser)
(options, args) = parser.parse_args()
if args:
print ("Error: script doesn't take any positional arguments")
sys.exit(1)
# system under test can be any CPU
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
# Match the memories with the CPUs, based on the options for the test system
TestMemClass = Simulation.setMemClass(options)
if options.benchmark:
try:
bm = Benchmarks[options.benchmark]
except KeyError:
print ("Error benchmark %s has not been defined.") %
options.benchmark
print ("Valid benchmarks are: %s") % DefinedBenchmarks
sys.exit(1)
else:
if options.dual:
bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
SysConfig(disk='linux-arm-ael.img', mem=options.mem_size)]
else:
bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
np = options.num_cpus
if len(bm) == 2:
drive_sys = build_drive_system(np)
test_sys = build_test_system(np)
# root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
root = makeDualRootPacketLoss(True, test_sys, drive_sys,
options.etherdump,
options.packet_loss_num,
options.packet_loss_base)
elif len(bm) == 1:
test_sys = build_test_system(np)
root = Root(full_system=True, system=test_sys)
else:
print ("Error I don't know how to create more than 2 systems.")
sys.exit(1)
if options.timesync:
root.time_sync_enable = False
if options.frame_capture:
VncServer.frame_capture = True
Simulation.setWorkCountOptions(test_sys, options)
Simulation.run(options, root, test_sys, FutureClass)
===================
-Mandi Das
On Wed, Oct 24, 2018 at 5:55 AM Ciro Santilli <[email protected]>
wrote:
> What's in fs_dvfs_4core.py? I cannot find it on master.
>
> Does it set system.iobus.forward_latency as the error suggests?
>
> Otherwise, get some config script from master working first, then
> bisect out the problem by looking at configs from m5out/config.ini.
>
> On Wed, Oct 24, 2018 at 9:25 AM Mandi Das <[email protected]> wrote:
> >
> > Hi,
> >
> > I'm trying to run full-system simulation and I'm stuck with the
> following error:
> > =================
> > Start simulation for m5out_vmlinux_vexpress_bbench_dvfs_4core
> > Wed Oct 24 04:23:06 EDT 2018
> > mkdir: cannot create directory
> ‘./m5out_vmlinux_vexpress_bbench_dvfs_4core’: File exists
> > gem5 Simulator System. http://gem5.org
> > gem5 is copyrighted software; use the --copyright option for details.
> >
> > gem5 compiled Oct 18 2018 01:07:59
> > gem5 started Oct 24 2018 04:23:06
> > gem5 executing on md3kq, pid 6638
> > command line: ./build/ARM/gem5.opt --debug-flags=DVFS,EnergyCtrl
> --debug-file=dfvs_debug.log -d ./m5out_vmlinux_vexpress_bbench_dvfs_4core
> /home/m/gem5/configs/example/fs_dvfs_4core.py --cpu-type=DerivO3CPU
> --mem-size=2048MB --machine-type=VExpress_EMM --num-cpus=4 --caches
> --l2cache --cacheline_size=64 --l1d_size=16kB --l1d_assoc=4 --l2_size=2MB
> --l2_assoc=8 --mem-type=LPDDR3_1600_1x32 --l1i_size=16kB --l1i_assoc=4
> --kernel=vmlinux --disk-image=android.img
> --dtb-filename=/dist/m5/system/binaries/vexpress-v2p-ca15-tc1-gem5_dvfs_4cpus.dtb
> --fast-forward=1000000000000 '--cpu-clock=[1 GHz,750 MHz,500 MHz]'
> --script=configs/boot/bbench-ics.rcS --frame-capture
> >
> > Global frequency set at 1000000000000 ticks per second
> > warn: rounding error > tolerance
> > 473.484848 rounded to 473
> > warn: rounding error > tolerance
> > 473.484848 rounded to 473
> > warn: DRAM device capacity (512 Mbytes) does not match the address range
> assigned (2048 Mbytes)
> > info: kernel located at: /dist/m5/system/binaries/vmlinux
> > warn: rounding error > tolerance
> > 473.484848 rounded to 473
> > fatal: system.iobus.forward_latency without default or user set value
> > End simulation for m5out_vmlinux_vexpress_bbench_dvfs_4core
> > Wed Oct 24 04:23:06 EDT 2018
> >
> > ====================
> >
> > Any help will be appreciated.
> > Thanks.
> >
> > -Mandi Das
> > _______________________________________________
> > gem5-users mailing list
> > [email protected]
> > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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