Hey Usman, Can you please provide a small program that I can use to reproduce this issue?
The CLFLUSH instruction only flushes the cache line till the request queue of the memory controller and not to memory. Intel had proposed and later decommissioned a PCOMMIT instruction which cleared the memory controller queues. So I think the load after a CLFLUSH would simply read the value from the memory controller queue itself. So the load latency might be similar to cache latency and not memory latency. I will look into this further. Cheers, Swapnil Haria, PhD Candidate, Dept of Computer Sciences, University of Wisconsin-Madison http://pages.cs.wisc.edu/~swapnilh/ On Wed, Oct 24, 2018 at 6:50 AM Usman Ali <[email protected]> wrote: > Dear, > > I am in scenario where I need simulator to generate different data read > time for memory and cache but I am getting constant reading time > irrespective data comes from memory and caches. > > I used clfush command to empty cache line, so that system reads from > memory. > > clflush cause cache misses in stats, but data reading time shows within > program that it comes from cache where data is coming from memory. [rdtsc > is used for time measurement ] > > I simulate program in Timings and Derive03 CPU but issue is still there. > Is this issue with 'clflush' implementation within x86 arch in GEM5? any > suggestion will be appreciated. > > PS: On real system, its working fine. > > regards, > > Usman Ali > MSEE Student, Information Technology Univeristy, Lahore > [email protected] > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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