Thanks a lot.
By the way, I want to know how to run regression tests. It seems the regression
test depends on SPEC CPU2000 heavily. I have the SPEC CPU2000 & 2006 suite. But
I still don't understand how to make it work...
The document site http://gem5.org/SPEC_benchmarks provides such information:
Workloads created from this package expect to find their binaries and input
files in the following two directories, respectively.
cpu2000/binaries/<isa>/<operating system>/<benchmark>
cpu2000/data/<benchmark>/<input set>
But there isn't an example. To my understanding, an example of the mcf
benchmark should be :
cpu2000/binaries/x86/linux/mcf
cpu2000/binaries/mcf/ref
cpu2000/binaries/mcf/ test
cpu2000/binaries/mcf/train
These are so-called directories. And there should be files in these
directories. For instance, cpu2000/binaries/x86/linux/mcf/mcf, the latter mcf
is a file.
Or maybe I should use cpu2000/binaries/x86/linux/mcf, just the mcf program, no
additional path.
I have tried both methods but failed.
The regress.py just throws:
AttributeError: /home/zheng/SPEC2000_v13/binaries/x86/linux/mcf not found.
But the file is just there. I don't know what happened.
BTW, I have a question about the naming methods of gem5: when to use UPPERCASE
in paths and file names? Sometimes, I need to use "X86", "ALPHA". While other
times I need to use "x86", "alpha". Frankly speaking, it is terrible!
Best Regards
Zheng Liang
EECS, Peking University
-----Original Messages-----
From:"Daniel Carvalho" <oda...@yahoo.com.br>
Sent Time:2018-11-10 22:51:56 (Saturday)
To: gem5-users@gem5.org, "梁政" <liangzh...@pku.edu.cn>
Cc:
Subject: Re: How to modify the Cache Timing Model ?
Hello Liang,
The cache timing model is something that me, Jason and Nikos have been recently
discussing. You can follow part of the discussion on the following links:
https://gem5-review.googlesource.com/c/public/gem5/+/13697 and
https://gem5-review.googlesource.com/c/public/gem5/+/13835.
Reworking the timing model to be more accurate and flexible is a hard task, and
you will likely just want to modify code related to timing, as the latency in
atomic mode is not well defined (in the sense of how correct it should be;
There is no clear answer). I'd suggest you to look at these patches and their
evolution to have and idea of the decisions that you may or may not want to
take (I am not saying they are the right way to do it, though).
Regarding the Tags, we currently have 3 sub-classes: BaseSetAssoc, FALRU and
SectorTags. Although we can think of FALRU as a subset of BaseSetAssoc (and you
can definitely create a full associative tag using BaseSetAssoc), FALRU has its
own implementation, which leverages from hashes and the awareness of a single
replacement policy (LRU), because otherwise the cost of checking every block
would be too high for greater cache sizes.
Regards,
Daniel
Em sexta-feira, 9 de novembro de 2018 22:00:59 GMT+1, 梁政
<liangzh...@pku.edu.cn> escreveu:
Hi
I am reading the latest code of gem5 and try to make the cache model more
flexible (e.g., allowing non-constant access latency). So I will change the
timing behavior of the Cache class.
Currently, I am reading the code in /mem/cache. I found that two major classes
have their timing model: the Cache/NoncoherentCache/BaseCache family and the
Tag family.
So what I need to do is to change related codes with a device timing model,
right? Or there may be other points I missed? Thanks for your advice.
BTW, what are the FALRU tags for? It seems all configurations use SetAssoc
Tags. I found a paper from UC.Berkeley. It is related to Sector Cache. Maybe
someone will use that model in the future. But why should Fully-associative LRU
cache be considered separately?
Regards
Zheng Liang
EECS, Peking University
_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
