Dear All,
We are using a single core configuration with L2 cache as last level cache.
We are finding it difficult to understand the total number of reads and
writes separately to L2 cache. Following are the stats i believe will be
relevant to find them out. Why does certain comments have read+write
accesses when some of the read access add up to the total.(for eg.
system.l2.ReadExReq_accesses::total +
system.l2.ReadSharedReq_accesses::switch_cpus.data =
system.l2.demand_accesses::switch_cpus.data). Does this means writes in
this case is 0 other than replacements in L2?
system.l2.WritebackDirty_accesses::writebacks 15027703
# number of WritebackDirty accesses(hits+misses)
system.l2.WritebackDirty_accesses::total 15027703
# number of WritebackDirty accesses(hits+misses)
system.l2.WritebackClean_accesses::writebacks 1252
# number of WritebackClean accesses(hits+misses)
system.l2.WritebackClean_accesses::total 1252
# number of WritebackClean accesses(hits+misses)
system.l2.ReadExReq_accesses::switch_cpus.data 366355
# number of ReadExReq accesses(hits+misses)
system.l2.ReadExReq_accesses::total 366355
# number of ReadExReq accesses(hits+misses)
system.l2.ReadCleanReq_accesses::switch_cpus.inst 1252
# number of ReadCleanReq accesses(hits+misses)
system.l2.ReadCleanReq_accesses::total 1252
# number of ReadCleanReq accesses(hits+misses)
system.l2.ReadSharedReq_accesses::switch_cpus.dtb.walker 6683608
# number of ReadSharedReq accesses(hits+misses)
system.l2.ReadSharedReq_accesses::switch_cpus.itb.walker 16059830
# number of ReadSharedReq accesses(hits+misses)
system.l2.ReadSharedReq_accesses::switch_cpus.data 27889091
# number of ReadSharedReq accesses(hits+misses)
system.l2.ReadSharedReq_accesses::total 50632529
# number of ReadSharedReq accesses(hits+misses)
system.l2.demand_accesses::switch_cpus.dtb.walker 6683608
# number of demand (read+write) accesses
system.l2.demand_accesses::switch_cpus.itb.walker 16059830
# number of demand (read+write) accesses
system.l2.demand_accesses::switch_cpus.inst 1252
# number of demand (read+write) accesses
system.l2.demand_accesses::switch_cpus.data 28255446
# number of demand (read+write) accesses
system.l2.demand_accesses::total 51000136
# number of demand (read+write) accesses
system.l2.overall_accesses::switch_cpus.dtb.walker 6683608
# number of overall (read+write) accesses
system.l2.overall_accesses::switch_cpus.itb.walker 16059830
# number of overall (read+write) accesses
system.l2.overall_accesses::switch_cpus.inst 1252
# number of overall (read+write) accesses
system.l2.overall_accesses::switch_cpus.data 28255446
# number of overall (read+write) accesses
system.l2.overall_accesses::total 51000136
# number of overall (read+write) accesses
system.l2.writebacks::writebacks 1324548
# number of writebacks
system.l2.writebacks::total 1324548
# number of writebacks
system.l2.replacements 2185528
# number of replacements
--
With Regards,
Varun Venkitaraman.
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